Thin film transistors with offset source and drain structures and process for forming such

Patent metadata

Field	Value
Publication number	US-11929415-B2
Application number	US-201916447880-A
Country	US
Kind code	B2
Filing date	Jun 20, 2019
Priority date	Jun 20, 2019
Publication date	Mar 12, 2024
Grant date	Mar 12, 2024

Abstract

A device is disclosed. The device includes a source contact and a drain contact, a first dielectric between the source contact and the drain contact, a channel under the source contact and the drain contact, and a gate electrode below the channel, the gate electrode in an area under the first dielectric that does not laterally extend under the source contact or the drain contact. A second dielectric is above the gate electrode and underneath the channel.

First claim

What is claimed is:

1. A device, comprising:
a source contact and a drain contact;
a first dielectric between the source contact and the drain contact, the first dielectric having an uppermost surface at a same level as an uppermost surface of the source contact and the drain contact;
a channel under the source contact and the drain contact;
a gate electrode below the channel, the gate electrode in an area under the first dielectric that does not laterally extend under the source contact or the drain contact;
a second dielectric above the gate electrode and underneath the channel; and
an interconnect layer beneath the gate electrode, the interconnect layer extending laterally beyond the source contact and the drain contact along a direction from the source contact to the drain contact.

2. The device of claim 1 , wherein the gate electrode includes a conductive via.

3. The device of claim 1 , further comprising an etch stop layer, wherein the gate electrode is formed in the etch stop layer.

4. The device of claim 1 , wherein the bottom of the gate electrode is directly connected to the interconnect layer.

5. The device of claim 1 , wherein the width of the gate electrode is from 20 to 40 nm.

6. The device of claim 1 , wherein the thickness of the gate electrode is from 10 to 30 nm.

7. The device of claim 1 , wherein the source contact and the drain contact include a plurality of layers of materials.

8. A system, comprising:
one or more processing components; and
one or more data storage components, the data storage components including at least one device, the at least one device including:
a source contact and a drain contact;
a first dielectric between the source contact and the drain contact, the first dielectric having an uppermost surface at a same level as an uppermost surface of the source contact and the drain contact;
a channel under the source contact and the drain contact;
a gate electrode below the channel, the gate electrode occupying an area under the first dielectric that does not laterally extend under the source contact or the drain contact;
a second dielectric above the gate electrode and underneath the channel; and
an interconnect layer beneath the gate electrode, the interconnect layer extending laterally beyond the source contact and the drain contact along a direction from the source contact to the drain contact.

9. The system of claim 8 , wherein the gate electrode includes a conductive via.

10. The system of claim 8 , further comprising an etch stop layer, wherein the gate electrode is formed in the etch stop layer.

11. The system of claim 8 , wherein the bottom of the gate electrode is directly connected to the interconnect layer.

12. The system of claim 8 , wherein the width of the gate electrode is from 20 to 40 nm.

13. The system of claim 8 , wherein the thickness of the gate electrode is from 10 to 30 nm.

14. The system of claim 8 , wherein the source contact and the drain contact include a plurality of layers of materials.

Assignees

• Intel Corp

Inventors

• Ku Chieh-Jen
• Wang Pei-Hua
• Sell Bernhard
• Lajoie Travis W

Classifications

• H10D30/031

  of thin-film transistors [TFT] · CPC title

• H10D64/258

  characterised by the relative positions of the source or drain electrodes with respect to the gate electrode · CPC title

• H10D30/6729

  characterised by the electrodes · CPC title

• H10D30/6713

  characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes · CPC title

• H10D30/6725

  having supplementary regions or layers for improving the flatness of the device · CPC title