Semiconductor devices having improved electrical characteristics and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-11929324-B2
Application number	US-202318133575-A
Country	US
Kind code	B2
Filing date	Apr 12, 2023
Priority date	Sep 16, 2019
Publication date	Mar 12, 2024
Grant date	Mar 12, 2024

Abstract

The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate including a first device isolation region, a second device isolation region having a first side and a second side opposite the first side, a first active region between the first device isolation region and the first side of the second device isolation region, and a second active region adjacent to the second side of the second device isolation region;
a first bit line structure on the first device isolation region;
a second bit line structure on the second active region;
a buffer pattern between the first device isolation region and the first bit line structure;
a first contact between the first bit line structure and the second bit line structure, the first contact including a first portion, a second portion that is on the first portion, and a third portion that is on the second portion;
a second contact between the second active region and the second bit line structure;
a first spacer structure between the first bit line structure and the first contact, the first spacer structure including a first sub-spacer, a second sub-spacer that is on the first sub-spacer, and a third sub-spacer that is on the second sub-spacer; and
a capacitor bottom electrode on the first contact,
wherein the first portion of the first contact is in contact with the first device isolation region, the first active region and the second device isolation region,
wherein the first sub-spacer of the first spacer structure is in contact with a top surface of the buffer pattern,
wherein the second sub-spacer of the first spacer structure is in contact with the buffer pattern, the first device isolation region and the first portion of the first contact, and
wherein a top surface of the first portion of the first contact is lower than a top surface of the first device isolation region.

2. The semiconductor device of claim 1 , wherein the first portion of the first contact includes one or more of metal, nitride, silicide, and/or polysilicon.

3. The semiconductor device of claim 1 , wherein the first portion of the first contact includes metal, silicide and polysilicon.

4. The semiconductor device of claim 1 , wherein the first portion of the first contact includes metal and silicide.

5. The semiconductor device of claim 1 , wherein the third sub-spacer of the first spacer structure is spaced apart from the first device isolation region and from the first portion of the first contact.

6. The semiconductor device of claim 1 , wherein the first portion of the first contact includes a concave surface, and
wherein the second portion of the first contact is in contact with the concave surface of the first portion of the first contact.

7. The semiconductor device of claim 1 , wherein the first portion of the first contact is in contact with a side surface of the first device isolation region and a top surface of the first active region.

8. The semiconductor device of claim 1 , further comprising a second spacer structure that is between the second bit line structure and the first contact, and
wherein the first portion of the first contact is in contact with the second spacer structure.

9. The semiconductor device of claim 1 , wherein a top surface of the third sub-spacer of the first spacer structure is lower than a top surface of the second sub-spacer of the first spacer structure, and
wherein a bottom surface of the third sub-spacer of the first spacer structure is higher than a bottom surface of the second sub-spacer of the first spacer structure.

10. The semiconductor device of claim 1 , wherein a top surface of the third sub-spacer of the first spacer structure is lower than a top surface of the first sub-spacer of the first spacer structure, and
wherein a bottom surface of the third sub-spacer of the first spacer structure is lower than a bottom surface of the first sub-spacer of the first spacer structure.

11. The semiconductor device of claim 1 , wherein a bottom surface of the second sub-spacer of the first spacer structure is lower than a bottom surface of the first sub-spacer of the first spacer structure.

12. The semiconductor device of claim 1 , wherein a width of the third portion of the first contact is greater than a width of the second portion of the first contact.

13. The semiconductor device of claim 1 , wherein a bottom surface of the first contact is higher than a bottom surface of the second contact.

14. The semiconductor device of claim 1 , wherein the first portion of the first contact is horizontally offset with respect to the second portion of the first contact.

15. The semiconductor device of claim 1 , wherein the first bit line structure includes a conductive pattern,
wherein the first sub-spacer of the first spacer structure is in contact with a side surface of the conductive pattern of the first bit line structure, and
wherein a bottom surface of the first sub-spacer of the first spacer structure is substantially coplanar with a bottom surface of the conductive pattern of the first bit line structure.

16. The semiconductor device of claim 1 , wherein a bottom surface of each of the second sub-spacer and the third sub-spacer of the first spacer structure is lower than the top surface of the first device isolation region.

17. A semiconductor device, comprising:
a substrate including a device isolation region and an active region;
a buffer pattern on the device isolation region;
a bit line structure on the buffer pattern;
a contact structure on the active region, the contact structure including a first portion, a second portion that is on the first portion, and a third portion that is on the second portion;
a spacer structure between the bit line structure and the contact structure, the spacer structure including a first spacer, a second spacer that is on the first spacer, and a third spacer that is on the second spacer; and
a capacitor bottom electrode on the contact structure,
wherein the first portion of the contact structure is in contact with a side surface of the device isolation region and a top surface of the active region,
wherein the first spacer of the spacer structure is in contact with a top surface of the buffer pattern,
wherein a top surface of the third spacer of the spacer structure is lower than a top surface of each of the first spacer and the second spacer of the spacer structure, and
wherein a bottom surface of each of the second spacer and the third spacer of the spacer structure is lower than a top surface of the device isolation region.

18. The semiconductor device of claim 17 , wherein the second spacer of the spacer structure is in contact with a side surface of the device isolation region and a top surface of the first portion of the contact structure.

19. A semiconductor device, comprising:
a substrate including a first device isolation region, a second device isolation region having a first side and a second side opposite the first side, a first active region between the first device isolation region and the first side of the second device isolation region, and a second active region adjacent to the second side of the second device isolation region;
a first bit line structure on the first device isolation region;
a second bit line structure on the second active region;
a buffer pattern between the first device isolation region and the first bit line structure;
a first contact between the first bit line structure and the second bit line structure, the first contact including a first portion, a second portion tha

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Taejin
• Kim Keunnam
• Park Sohyun
• Chun Jin-Hwan
• Choi Wooyoung
• Han Sunghee
• Heo Inkyoung
• Hwang Yoosang

Classifications

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/43 Primary

  Layouts of interconnections · CPC title

• H10D84/0184

  Manufacturing their gate sidewall spacers · CPC title

• H10D84/0191 Primary

  Manufacturing their doped wells · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title