Chip package structure and method for manufacturing the same, and module

Patent metadata

Field	Value
Publication number	US-11929313-B2
Application number	US-202117532248-A
Country	US
Kind code	B2
Filing date	Nov 22, 2021
Priority date	Jun 30, 2021
Publication date	Mar 12, 2024
Grant date	Mar 12, 2024

Abstract

A chip package structure, manufacturing method thereof, and module are described. In an embodiment, the chip package structure includes: a substrate, a wiring layer, a chip, and a second conductive bump, wherein, in an embodiment, the substrate includes a first region and a second region surrounding the first region, and the wiring layer is located on side of the substrate and includes metal wire, wherein at least part of a metal wire is in contact with the substrate in direction perpendicular to the substrate, and the metal wire overlaps with the second region, wherein the chip is located on side of the wiring layer facing away from the substrate, and the chip corresponds to the first region. In an embodiment, a first conductive bump is provided on side of the chip facing away from the substrate and is electrically connected to the metal wire.

First claim

What is claimed is:

1. A chip package structure, comprising:
a substrate comprising a first region and a second region surrounding the first region;
a wiring layer located on a side of the substrate and comprising at least one metal wire, wherein at least part of a metal wire of the at least one metal wire is in contact with the substrate, and wherein the at least one metal wire overlaps with the second region in a direction perpendicular to the substrate;
a chip located on a side of the wiring layer facing away from the substrate, wherein the chip corresponds to the first region, wherein the chip comprises a first conductive bump disposed on a side of the chip facing towards to the substrate, and wherein the first conductive bump is electrically connected to one of the at least one metal wire; and
a second conductive bump electrically connected to one of the at least one metal wire, wherein the second conductive bump does not overlap with the chip in the direction perpendicular to the substrate;
wherein the chip comprises a photosensitive region located at the side of the chip facing towards the substrate and opposite to the first region, and wherein the photosensitive region does not overlap with the metal wire in the wiring layer.

2. The chip package structure of claim 1 , further comprising:
a light-shielding portion located on a side of the substrate facing towards the chip or a side of the substrate facing away from the chip,
wherein an orthographic projection of the light-shielding portion on a plane of the photosensitive region surrounds the photosensitive region and does not overlap with the photosensitive region.

3. The chip package structure of claim 1 , further comprising:
a filling adhesive filled on periphery edges of the chip and in contact with the wiring layer.

4. The chip package structure of claim 1 , further comprising:
an encapsulation layer, wherein the second conductive bump comprises a first end and a second end that are connected to each other, wherein the first end is located at a side of the second end away from the substrate; and the encapsulation layer encapsulates the chip, wherein the second end is embedded in the encapsulation layer, and wherein the first end is exposed outside the encapsulation layer.

5. The chip package structure of claim 1 , further comprising:
an encapsulation layer, wherein a surface of the second conductive bump faces away from the substrate is a plane, wherein the encapsulation layer encapsulates the chip, wherein the second conductive bump is embedded in the encapsulation layer, and wherein the encapsulation layer exposes the surface of the second conductive bump facing away from the substrate.

6. The chip package structure of claim 1 , wherein the wiring layer comprises an insulating layer, and wherein the insulating layer overlaps with the first region and the second region in the direction perpendicular to the substrate.

7. The chip package structure of claim 1 , wherein the wiring layer comprises an insulating layer having a hollow region, and wherein the hollow region overlaps with the first region in the direction perpendicular to the substrate.

8. The chip package structure of claim 1 , wherein the substrate comprises a glass substrate.

9. The chip package structure of claim 8 , wherein the substrate further comprises a filter layer located on a side of the glass substrate facing towards the wiring layer.

10. The chip package structure of claim 8 , wherein the substrate further comprises a filter layer located on a side of the glass substrate facing away from the wiring layer.

11. The chip package structure of claim 1 , wherein the substrate has a thickness d, where 0.05 mm≤d≤0.7 mm.

12. The chip package structure of claim 1 , wherein the at least one metal wire comprises a plurality of metal wires, wherein the second conductive bump corresponds to a metal wire of the plurality of metal wires, and wherein orthographic projections of metal wires of the plurality of metal wires on the substrate surround the first region.

13. A module, comprising:
a circuit board;
a chip package structure, comprising:
a substrate comprising a first region and a second region surrounding the first region;
a wiring layer located on a side of the substrate and comprising at least one metal wire, wherein at least part of a metal wire of the at least one metal wire is in contact with the substrate, and wherein the at least one metal wire overlaps with the second region in a direction perpendicular to the substrate;
a chip located on a side of the wiring layer facing away from the substrate, wherein the chip corresponds to the first region, wherein the chip comprises a first conductive bump provided on a side of the chip facing towards to the substrate, and wherein the first conductive bump is electrically connected to a metal wire of the at least one metal wire; and
a second conductive bump electrically connected to a metal wire of the at least one metal wire, wherein the second conductive bump does not overlap with the chip in the direction perpendicular to the substrate, and wherein the chip package structure is electrically connected to the circuit board through the second conductive bump;

a control chip fixed on the circuit board;
a passive device fixed on the circuit board;
a lens group located at a side of the substrate facing away from the chip, wherein the lens group overlaps with the chip in the direction perpendicular to the substrate; and
a focus motor configured to drive lenses of the lens group to make a relative movement;
wherein the chip comprises a photosensitive region located at the side of the chip facing towards the substrate and opposite to the first region, and wherein the photosensitive region does not overlap with the metal wire in the wiring layer.

14. A method for manufacturing a chip package structure, comprising:
providing a substrate, the substrate comprising a first region and a second region surrounding the first region;
fabricating a wiring layer on the substrate by a film forming process, wherein the wiring layer comprises at least one metal wire, wherein at least part of a metal wire of the at least one metal wire is in contact with the substrate, and wherein the at least one metal wire overlaps with the second region in a direction perpendicular to the substrate;
providing a chip with a first conductive bump arranged on a side of the chip;
attaching the wiring layer and the chip with the first conductive bump, wherein the chip corresponds to the first region, and wherein the first conductive bump is electrically connected to a metal wire of the at least one metal wire; and
fabricating a second conductive bump, wherein the second conductive bump is electrically connected to a metal wire of the at least one metal wire;
wherein the chip comprises a photosensitive region located at the side of the chip facing towards the substrate and opposite to the first region, and wherein the photosensitive region does not overlap with the metal wire in the wiring layer.

15. The method for manufacturing a chip package structure according to claim 14 , wherein the chip comprises a photosensitive region; and
wherein said providing the chip comprises:
providing a chip matrix and fabricating the first conductive bump on a side of the chip matrix comprising the photosensitive region, and
providing the chip matrix and thinning a back side of the photosensitive region of the chip matrix to thin the chip matrix.

16. The method for manufacturing a chip package structure according to claim 14 , wherein the wiring

Assignees

• Shanghai Tianma Micro Elect Co

Inventors

• Wang Mingyu
• Xi Kerui
• Peng Xuhui
• Qin Feng
• Zhang Jie

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W70/681

  comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title