Plurality of lead frames for cooling a power device

Patent metadata

Field	Value
Publication number	US-11929307-B2
Application number	US-202017429464-A
Country	US
Kind code	B2
Filing date	Jan 15, 2020
Priority date	Feb 13, 2019
Publication date	Mar 12, 2024
Grant date	Mar 12, 2024

Abstract

A power semiconductor module, which is a semiconductor device, includes a semiconductor element 155 and a lead frame 318 that is disposed to face the semiconductor element 155 and connected to the semiconductor element 155 by a solder material 162 . The lead frame 318 has the top surface 331 including a surface facing the semiconductor element 155 , and the side surface 334 connected to the peripheral edge portion 333 of the top surface 331 at a predetermined angle with respect to the top surface 331 . The top surface of the lead frame 318 includes the solder surface 332 that is in contact with the solder material 162 and the solder resistance surface on which the solder material 162 is less wettable than on the solder surface 332 . The solder resistance surface is formed to surround the periphery of the solder surface 332 . In this manner, when the semiconductor element and the lead frame are solder-joined in the semiconductor device, the region where the solder wet-spreads is appropriately controlled.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a semiconductor element; and
a first lead frame that is disposed to face the semiconductor element and is connected to the semiconductor element by a first solder material,
wherein
the first lead frame includes a top surface including a surface facing the semiconductor element, and a side surface connected to a peripheral edge portion of the top surface at a predetermined angle with respect to the top surface,
the top surface of the first lead frame includes a solder surface that is in contact with the first solder material and a solder resistance surface on which the first solder material is less wettable than on the solder surface, and
the solder resistance surface is formed to surround periphery of the solder surface;
wherein:
the side surface of the first lead frame is connected to a peripheral edge portion of the top surface with a curved surface formed with a radius interposed therebetween, and
the solder resistance surface is formed to include the curved surface.

2. The semiconductor device according to claim 1 , further comprising:
a second lead frame connected to the semiconductor element by a second solder material,
wherein
the semiconductor element has a pair of surfaces parallel to each other, a first electrode surface provided on a surface on one side of the pair of surfaces, and a second electrode surface provided on a surface on the other side,
the first lead frame is disposed to face the first electrode surface, and is connected to the first electrode surface of the semiconductor element by the first solder material, and
the second lead frame is disposed to face the second electrode surface, and is connected to the second electrode surface of the semiconductor element by the second solder material.

3. The semiconductor device according to claim 1 , wherein
an oxide film is formed on the solder resistance surface.

4. The semiconductor device according to claim 3 , wherein
the oxide film has a thickness of 1 nm or more.

5. The semiconductor device according to claim 1 , wherein
a processing trace is formed on the solder surface of the top surface, the processing trace obtained when removal processing of the top surface is performed.

6. The semiconductor device according to claim 5 , wherein
the removal processing is laser processing.

7. A semiconductor device comprising:
a semiconductor element; and
a first lead frame that is disposed to face the semiconductor element and is connected to the semiconductor element by a first solder material,
wherein
the first lead frame includes a top surface including a surface facing the semiconductor element, and a side surface connected to a peripheral edge portion of the top surface at a curved surface with respect to the top surface,
the top surface of the first lead frame includes a solder surface that is in contact with the first solder material and a solder resistance surface on which the first solder material is less wettable than on the solder surface, and surface;
the solder resistance surface is formed to surround periphery of the solder wherein an oxide film is formed on the solder resistance surface.

Assignees

• Hitachi Astemo Ltd

Inventors

• Takagi Yusuke
• TERAYAMA Ryo
• HAMAYA Ko
• Ikeda Osamu

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W74/01

  Manufacture or treatment · CPC title

• H10W70/466

  Tape carriers or flat leads · CPC title

• H10W70/461

  specially adapted for cooling · CPC title