Sense amplifier, memory, and method for controlling sense amplifier

Patent metadata

Field	Value
Publication number	US-11929112-B2
Application number	US-202117472792-A
Country	US
Kind code	B2
Filing date	Sep 13, 2021
Priority date	Jul 27, 2020
Publication date	Mar 12, 2024
Grant date	Mar 12, 2024

Abstract

The sense amplifier includes: an amplification module configured to amplify a voltage transmitted by a bit line or a reference bit line, when the sense amplifier is at an amplification stage; a first switch module configured to control the amplification module to be disconnected from the reference bit line, when the sense amplifier performs a read operation for the bit line and is at the amplification stage. In the disclosure, the power consumption of the sense amplifier may be reduced.

First claim

The invention claimed is:

1. A sense amplifier, comprising:
an amplification circuit configured to amplify a voltage transmitted by a bit line or a reference bit line, when the sense amplifier is at an amplification stage;
a first switch circuit configured to control the amplification circuit to be disconnected from the reference bit line, when the sense amplifier performs a read operation on the bit line and the sense amplifier is at the amplification stage; and
a discharge control circuit configured to discharge the sense amplifier after the sense amplifier performs a read ‘1’ operation on the bit line.

2. The sense amplifier of claim 1 , wherein the first switch circuit is configured to control the amplification circuit to be disconnected from the reference bit line based on a data source control signal, when the sense amplifier is at the amplification stage.

3. The sense amplifier of claim 2 , wherein the first switch circuit comprises:
a first switch assembly, a first control terminal of the first switch assembly being configured to receive the data source control signal, a first terminal of the first switch assembly being connected to the amplification circuit through a first node, and a second terminal of the first switch assembly being connected to the reference bit line.

4. The sense amplifier of claim 3 , wherein the first switch circuit configured to control the amplification circuit to be disconnected from the reference bit line based on the data source control signal is configured to:
control the amplification circuit to be disconnected from the reference bit line in response to the data source control signal and a first control signal; and
wherein the first switch assembly further comprises a second control terminal configured to receive the first control signal.

5. The sense amplifier of claim 4 , wherein the first switch assembly comprises:
a fourth negative channel Metal Oxide Semiconductor (NMOS) transistor, a gate of the fourth NMOS transistor being configured to receive the data source control signal, a source of the fourth NMOS transistor being connected to the reference bit line, and a drain of the fourth NMOS transistor being connected to the first node; and
a fourth positive channel Metal Oxide Semiconductor (PMOS) transistor, a gate of the fourth PMOS transistor being configured to receive the first control signal, a drain of the fourth PMOS transistor being connected to the reference bit line, and a source of the fourth PMOS transistor being connected to the first node.

6. The sense amplifier of claim 3 , wherein the first switch assembly comprises:
a fourth negative channel Metal Oxide Semiconductor (NMOS) transistor, a gate of the fourth NMOS transistor being configured to receive the data source control signal, a source of the fourth NMOS transistor being connected to the reference bit line, and a drain of the fourth NMOS transistor being connected to the first node.

7. The sense amplifier of claim 1 , wherein the sense amplifier further comprises:
a second switch circuit configured to control the amplification circuit to be disconnected from the bit line, when the sense amplifier performs a read operation on the reference bit line and the sense amplifier is at the amplification stage.

8. The sense amplifier of claim 7 , wherein the second switch circuit comprises:
an inverter, an input terminal of the inverter being configured to receive a data source control signal; and
a second switch assembly, a first control terminal of the second switch assembly being connected to an output terminal of the inverter, a first terminal of the second switch assembly being connected to the amplification circuit through a second node, and a second terminal of the second switch assembly being connected to the bit line.

9. The sense amplifier of claim 8 , wherein the second switch assembly further comprises:
a second control terminal configured to receive a first control signal.

10. The sense amplifier of claim 9 , wherein the second switch assembly comprises:
a fifth negative channel Metal Oxide Semiconductor (NMOS) transistor, a gate of the fifth NMOS transistor being connected to the output terminal of the inverter, a drain of the fifth NMOS transistor being connected to the bit line, and a source of the fifth NMOS transistor being connected to the second node; and
a fifth positive channel Metal Oxide Semiconductor (PMOS) transistor, a gate of the fifth PMOS transistor being configured to receive the first control signal, a source of the fifth PMOS transistor being connected to the bit line, and a drain of the fifth PMOS transistor being connected to the second node.

11. The sense amplifier of claim 8 , wherein the second switch assembly comprises:
a fifth negative channel Metal Oxide Semiconductor (NMOS) transistor, a gate of the fifth NMOS transistor being connected to the output terminal of the inverter, a drain of the fifth NMOS transistor being connected to the bit line, and a source of the fifth NMOS transistor being connected to the second node.

12. The sense amplifier of claim 1 , wherein the amplification circuit comprises:
a first positive channel Metal Oxide Semiconductor (PMOS) transistor, a drain of the first PMOS transistor being connected to a first node;
a first negative channel Metal Oxide Semiconductor (NMOS) transistor, a drain of the first NMOS transistor being connected to the first node, and a gate of the first NMOS transistor being connected to a gate of the first PMOS transistor;
a second PMOS transistor, a drain of the second PMOS transistor being connected to a second node;
a second NMOS transistor, a drain of the second NMOS transistor being connected to the second node, and a gate of the second NMOS transistor being connected to a gate of the second PMOS transistor;
a third PMOS transistor, a drain of the third PMOS transistor being connected to a source of the first PMOS transistor and a source of the second PMOS transistor, a gate of the third PMOS transistor being configured to receive a second control signal, and a source of the third PMOS transistor being configured to receive a supply voltage; and
a third NMOS transistor, a drain of the third NMOS transistor being connected to a source of the first NMOS transistor and a source of the second NMOS transistor, a gate of the third NMOS transistor being configured to receive a first control signal, and a source of the third NMOS transistor being grounded;
wherein the gate of the first PMOS transistor is connected to the second node, and the gate of the second PMOS transistor is connected to the first node.

13. The sense amplifier of claim 12 , wherein the discharge control circuit comprises:
a first discharge assembly configured to connect the gate of the first NMOS transistor to the first node in response to a discharge control signal; and
a second discharge assembly configured to connect the gate of the second NMOS transistor to the second node in response to the discharge control signal.

14. The sense amplifier of claim 1 , further comprising:
a precharge circuit configured to precharge the bit line and the reference bit line when the sense amplifier is at a precharge stage.

15. A memory, comprising a sense amplifier, wherein the sense amplifier comprises:
an amplification circuit configured to amplify a voltage transmitted by a bit line or a reference bit line, when the sense amplifier is at an amplification stage;
a first switch circuit configured to control the amplification circuit to be disconnected from the reference bit line, when the sense amplifier performs a read operation on

Assignees

• Univ Anhui
• Changxin Memory Tech Inc

Inventors

• Peng Chunyu
• Wang Zijian
• Lu Wenjuan
• Wu Xiulong
• He Jun
• Li Xin
• Ying Zhan
• Cao Kanyu
• Lin Zhiting
• Chen Junning

Classifications

• G11C11/4091 Primary

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C5/06

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title

• G11C11/4094

  Bit-line management or control circuits · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C11/4099

  Dummy cell treatment; Reference voltage generators · CPC title