Synchronisation for a multi-tile processing unit

Patent metadata

Field	Value
Publication number	US-11928523-B2
Application number	US-202117446681-A
Country	US
Kind code	B2
Filing date	Sep 1, 2021
Priority date	Jul 14, 2021
Publication date	Mar 12, 2024
Grant date	Mar 12, 2024

Abstract

A multi-tile processing unit in which the tiles in the processing unit may be divided between two or more different external sync groups for performing barrier synchronisations. In this way, different sets of tiles of the same processing unit each sync with different sets of tiles external to that processing unit.

First claim

The invention claimed is:

1. A processing device comprising a processing unit comprising a plurality of processors, wherein the plurality of processors comprises a first set of processors and a second set of processors,
wherein each processor of the first set of processors is configured to participate in a first barrier synchronisation enforced between a first synchronisation group comprising the first set of processors and a third set of processors belonging to a first further processing device, wherein the first barrier synchronisation separates a compute phase for the first synchronisation group from a first exchange phase for the first synchronisation group,
wherein each of at least some of the processors of the first set of processors is configured to, during the first exchange phase, exchange data with the third set of processors,
wherein each processor of the second set of processors is configured to participate in a second barrier synchronisation enforced between a second synchronisation group comprising the second set of processors and a fourth set of processors belonging to a second further processing device, wherein the second barrier synchronisation separates a compute phase for the second synchronisation group from a second exchange phase for the second synchronisation group,
wherein each of at least some of the processors of the second set of processors is configured to, during the second exchange phase, exchange data with the fourth set of processors,
wherein the first exchange phase overlaps in time with the second exchange phase, and
wherein the processing device comprises an external sync controller comprising circuitry configured to:
coordinate the first barrier synchronisation between processors of the first synchronisation group by exchanging first sync messages with the first further processing device; and
coordinate the second barrier synchronisation between processors of the second synchronisation group by exchanging second sync messages with the second further processing device.

2. The processing device of claim 1 , wherein the first further processing device to which the third set of processors belongs is different to the second further processing device to which the fourth set of processors belongs.

3. The processing device of claim 1 , wherein the first further processing device to which the third set of processors belongs is the same as the second further processing device to which the fourth set of processors belongs.

4. The processing device of claim 1 , wherein each processor of the first set of processors and the second set of processors is configured to:
following the first exchange phase and the second exchange phase, participate in a third barrier synchronisation involving a third synchronisation group comprising the first set of processors and the second set of processors; and
following the third barrier synchronisation, participate in one or more further barrier synchronisations involving one or more new synchronisation groups different to the first synchronisation group, the second synchronisation group, and the third synchronisation group.

5. The processing device of claim 1 , wherein the first sync messages comprise a first sync request and sync acknowledgment pair, wherein the second sync messages comprises a second sync request and sync acknowledgment pair.

6. The processing device of claim 1 , wherein the external sync controller comprises storage holding configuration settings for:
determining a first destination to which at least one of the first sync messages for coordinating the first barrier synchronisation is sent; and
determining a second destination to which at least one of the second sync messages for coordinating the second barrier synchronisation is sent.

7. The processing device of claim 1 , wherein the circuitry of the external sync controller is configured to:
receive a first at least one sync request from the first set of processors indicating that the first set of processors has reached the first barrier synchronisation;
in response to the first at least one sync request, provide a sync acknowledgment to each of the first set of processors so as to cause each of the first set of processors to enter the first exchange phase, wherein the first sync messages include the first at least one sync request;
receive a second at least one sync request from the second set of processors indicating that the second set of processors has reached the second barrier synchronisation; and
in response to the second at least one sync request, provide a sync acknowledgment to each of the second set of processors so as to cause each of the second set of processors to enter the second exchange phase, wherein the second sync messages include the second at least one sync request.

8. The processing device of claim 1 , wherein at least some of the plurality of processors belong to multiple different synchronisation groups used for participating in different barrier synchronisations.

9. The processing device of claim 8 , wherein each of the plurality of processors comprises a register storing indications as to which of a plurality of synchronisation groups the respective processor belongs to.

10. The processing device of claim 1 , wherein each of the plurality of processors has a plurality of wires, wherein each of at least some of the plurality of wires is associated with a different one of a plurality of synchronisation groups,
wherein each of the processors of the first set of processors is configured to, upon reaching the first barrier synchronisation in its compiled code, assert a sync request signal on one of the respective plurality of wires that is associated with the first synchronisation group,
wherein each of the processors of the second set of processors is configured to, upon reaching the second barrier synchronisation in its compiled code, assert a sync request signal on one of the respective plurality of wires that is associated with the second synchronisation group.

11. The processing device of claim 10 , wherein each of the plurality of processors is configured to continually assert a sync request signal on any of the plurality of wires associated with synchronisation groups to which the respective processor does not belong.

12. The processing device of claim 1 , wherein each of at least some of the first set of processors is configured to select the first synchronisation group for the first barrier synchronisation by executing a sync instruction comprising an operand identifying the first synchronisation group.

13. The processing device of claim 12 , wherein the operand identifies the first synchronisation group by identifying a configurable synchronisation zone supporting synchronisations for the first synchronisation group.

14. The processing device of claim 1 , wherein the first synchronisation group is associated with a first synchronisation zone that is configurable based on settings held in each of the plurality of the processors to comprise different groupings of the plurality of processors, wherein the second synchronisation group is associated with a second synchronisation zone that is configurable based on the settings held in each of plurality of the processors to comprise different grouping of the plurality of processors.

15. The processing device of claim 1 , wherein the processing device is an integrated circuit, wherein the first further processing device is a first further integrated circuit, wherein the second further processing device is a second further integrated circuit.

16. The processing device of claim 1 , wherein

Assignees

• Graphcore Ltd

Inventors

• Knowles Simon
• Wilkinson Daniel John Pelham
• Alexander Alan
• Felix Stephen
• Osborne Richard
• Lacey David
• Huse Lars Paul

Classifications

• G06F9/522 Primary

  Barrier synchronisation · CPC title

• G06F9/30087

  Synchronisation or serialisation instructions · CPC title

• G06F9/3858

  Result writeback, i.e. updating the architectural state or memory · CPC title

• G06F1/12

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• G06F15/17325

  Synchronisation; Hardware support therefor (intertask synchronisation G06F9/52) · CPC title