PCIe device

Patent metadata

Field	Value
Publication number	US-11928070-B2
Application number	US-202117506610-A
Country	US
Kind code	B2
Filing date	Oct 20, 2021
Priority date	Apr 13, 2021
Publication date	Mar 12, 2024
Grant date	Mar 12, 2024

Abstract

A peripheral component interconnect express (PCIe) device includes a common function performing operations associated with a PCIe interface according to a function type, the common function being programmable to be a function type selected from a plurality function types, an access identification information controller generating first access identification information for allowing an access to the common function, and providing the first access identification information to an assigned system image to which the common function has been assigned, a data packet receiver receiving a data packet including target identification information indicating a target system image from the target system image, and an access allowance determiner determining whether or not to allow the target system image to access the common function based on the first access identification information and the target identification information.

First claim

What is claimed is:

1. A peripheral component interconnect express (PCIe) device, the PCIe device comprising:
a plurality of common functions performing operations associated with a PCIe interface according to a function type, each of the plurality of common functions being programmable to be a function type selected from a plurality function types,
wherein a common function of the plurality of common functions comprises:
an access identification information controller generating first access identification information for allowing an access to the common function, and providing the first access identification information to an assigned system image to which the common function has been assigned;
a data packet receiver receiving a data packet including target identification information indicating a target system image from the target system image;
an access allowance determiner determining whether or not to allow the target system image to access the common function based on the first access identification information and the target identification information; and
an operation controller processing the data packet received from the data packet receiver based on the determination of the access allowance.

2. The PCIe device of claim 1 , wherein the function type is one of a physical function (PF) type, a virtual function (VF) type, and a disable function type in which the operations are disabled.

3. The PCIe device of claim 1 , wherein the PCIe device further comprises a function type controller determines the function type of the common function by changing values of registers included in a configuration space of the common function.

4. The PCIe device of claim 1 , wherein the access identification information controller generates a random number according to a random number generation scheme, generates the first access identification information based on the random number, and stores the first access identification information.

5. The PCIe device of claim 1 , wherein the target identification information is included in a prefix of the data packet.

6. The PCIe device of claim 1 , wherein the access allowance determiner allows the target system image to access the common function when the first access identification information and the target identification information are consistent with each other, or
the access allowance determiner provides completer abort (CA) information to the target system image when the first access identification information and the target identification information are not consistent with each other.

7. The PCIe device of claim 1 , wherein the access identification information controller generates second access identification information at a predetermined time after generating the first access identification information, stores the second access identification information, and provides the second access identification information to the assigned system image.

8. A Peripheral Component Interconnect Express (PCIe) device, the PCIe device comprising:
a plurality of physical functions respectively enabled or disabled according to respective operation modes, the operation modes respectively being set to one of an active mode and an inactive mode,
wherein a physical function of the plurality of physical functions comprises:
an access identification information controller generating first access identification information for allowing an access to the physical function, and providing the first access identification information to an assigned system image to which the physical function has been assigned;
a data packet receiver receiving a data packet including target identification information indicating a target system image from the target system image;
an access allowance determiner determining whether or not to allow the target system image to access the physical function based on the first access identification information and the target identification information; and
an operation controller processing the data packet received from the data packet receiver based on determination of the access allowance.

9. The PCIe device of claim 8 , wherein the PCIe device further comprises a function mode controller setting the operation mode based on a function mode control information received from the host.

10. The PCIe device of claim 8 , wherein the access identification information controller generates a random number according to a random number generation scheme, generates the first access identification information based on the random number, and stores the first access identification information.

11. The PCIe device of claim 8 , wherein the target identification information is included in a prefix of the data packet.

12. The PCIe device of claim 8 , wherein the access allowance determiner allows the target system image to access the physical function when the first access identification information and the target identification information are consistent with each other, or
the access allowance determiner provides completer abort (CA) information to the target system image when the first access identification information and the target identification information are not consistent with each other.

13. The PCIe device of claim 8 , wherein the access identification information controller generates second access identification information at a predetermined time after generating the first access identification information, stores the second access identification information, and provides the second access identification information to the assigned system image.

14. A peripheral component interconnect express (PCIe) device, comprising:
a plurality of common functions performing operations associated with a PCIe interface according to a function type of each of the plurality of common functions, each of the plurality of common functions being programmable to be a function type selected from a plurality function types; and
a function mode controller setting operation modes of the plurality of common functions based on function mode control information provided from a host, each of the operation modes being set to one of an active mode and an inactive mode,
wherein a common function of the plurality of common functions is configured to generate access identification information for allowing an access to the common function, receive a data packet including target identification information indicating a target system image from the target system image, compare the access identification information and the target identification information, and process the data packet based on a comparison result.

15. The PCIe device of claim 14 , wherein the common function of the plurality of common functions comprises:
a configuration space including registers for configuring the common function to perform the operations; and
an operation controller controlling the common function to perform the operations according to the function type of the common function.

16. The PCIe device of claim 15 , wherein the PCIe device further comprises a function type controller determining the function type of each of the plurality of common functions as being one of a physical function (PF) type, a virtual function (VF) type, and a base function type based on function type setting information provided from the host.

17. The PCIe device of claim 16 , wherein the function type controller determines a function type of the common function from among a plurality of a function types by changing values of the registers included in the configuration space of the common function based on th

Assignees

• Sk Hynix Inc

Inventors

• Jeon Yong Tae
• Kang Byung Cheol
• Cho Seung Duk
• Yoon Sang Hyun
• Han Se Hyeon
• Jang Jae Young

Classifications

• G06F13/4221 Primary

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• G06F1/08

  Clock generators with changeable or programmable clock frequency · CPC title

• G06F7/588

  Random number generators, i.e. based on natural stochastic processes · CPC title

• G06F13/4045 Primary

  where the bus bridge performs an extender function · CPC title

• G06F1/3209

  Monitoring remote activity, e.g. over telephone lines or network connections · CPC title