Serial management interface with improved reliability

Patent metadata

Field	Value
Publication number	US-11928019-B2
Application number	US-202217902096-A
Country	US
Kind code	B2
Filing date	Sep 2, 2022
Priority date	Nov 21, 2018
Publication date	Mar 12, 2024
Grant date	Mar 12, 2024

Abstract

A first serial management interface device includes one or more input/output pins and a controller coupled to the one or more input/output pins. The controller receives a first frame from a second serial management interface device via a first input/output pin and generates a first error code based on the first frame received from the second serial management interface device. The controller receives a second frame from the second serial management interface device via a second input/output pin subsequent to receiving the first frame. The second frame includes a second error code. The controller compares the first error code to the second error code to determine whether first error code and the second error code match.

First claim

What is claimed is:

1. A first serial management interface device comprising:
one or more input/output pins; and
a controller coupled to the one or more input/output pins and configured to:
receive a first frame from a second serial management interface device via a first input/output pin;
generate a first error code based on the first frame received from the second serial management interface device;
receive a second frame from the second serial management interface device via a second input/output pin subsequent to receiving the first frame, the second frame including a second error code; and
compare the first error code to the second error code to determine whether first error code and the second error code match.

2. The first serial management interface device of claim 1 wherein the controller is configured to determine that the first frame is correctly received when the first error code and the second error code match.

3. The first serial management interface device of claim 1 wherein the controller is configured to discard the first frame when the first error code and the second error code do not match.

4. The first serial management interface device of claim 1 further comprising a register coupled to the controller wherein the controller is configured to write data received in the first frame to the register when the first error code and the second error code match.

5. The first serial management interface device of claim 1 wherein the first input/output pin is the same as the second input/output pin.

6. The first serial management interface device of claim 1 further comprising a register coupled to the controller wherein the controller is configured to send a third frame including data read from the register to the second serial management interface device via one of the one or more input/output pins in response to receiving the first frame.

7. The first serial management interface device of claim 6 wherein the controller is configured to generate a third error code based on data in the third frame and send a fourth frame including the third error code to the second serial management interface device via one of the one or more input/output pins.

8. The first serial management interface device of claim 7 wherein the third error code is further based on a portion of the fourth frame.

9. The first serial management interface device of claim 7 wherein the controller is configured to generate the third and fourth frames in a frame format compliant with one of Clause 22 and Clause 45 of IEEE 802.3-2018.

10. A system comprising:
the first and second serial management interface devices of claim 7 ;
wherein the second serial management interface device comprises a second controller configured to:
generate a fourth error code based on the third frame received from the first serial management interface device; and
verify whether the data received in the third frame is correct based on whether the fourth error code matches the third error code in the fourth frame received from the first serial management interface device.

11. A system comprising:
the first and second serial management interface devices of claim 6 ;
wherein the second serial management interface device comprises:
second input/output pins;
a second register; and
a second controller configured to receive the third frame from the first serial management interface device via one of the second input/output pins and to write the data received in the third frame to the second register without verification.

12. The system of claim 11 wherein writing the data to the second register without verification includes writing the data to the second register without receiving a fourth frame from the first serial management interface device including a third error code generated based on the third frame.

Assignees

• Marvell Asia Pte Ltd

Inventors

• Wu Dance
• Zhou Chuanhai
• Chou Hong Yu

Classifications

• G06F11/1004 Primary

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title