Electronic device for performing beamforming-based communication, and method therefor

Patent metadata

Field	Value
Publication number	US-11924787-B2
Application number	US-201917418522-A
Country	US
Kind code	B2
Filing date	Dec 12, 2019
Priority date	Dec 31, 2018
Publication date	Mar 5, 2024
Grant date	Mar 5, 2024

Abstract

An electronic device includes a housing, at least one antenna array disposed in the housing or formed on a part of the housing and including a plurality of antenna elements, a processor electrically or operatively connected to the antenna array, and a memory operatively connected to the at least one processor. In addition to the above, various embodiments identified through the specification are possible.

First claim

The invention claimed is:

1. An electronic device comprising:
a memory;
an antenna array including a plurality of conductive plates; and
a processor operatively connected to the memory and the antenna array,
wherein the processor is configured to:
receive a plurality of synchronization signal blocks corresponding to a plurality of transmit beams from a base station by using at least one first receive beam formed using one of the plurality of conductive plates;
identify at least one of the plurality of synchronization signal blocks received by using the first receive beam based at least in part on reception strengths of the plurality of synchronization signal blocks;
receive the at least one identified synchronization signal block by using each of a plurality of second receive beams formed using the plurality of conductive plates; and
determine one synchronization signal block among the at least one identified synchronization signal block based at least in part on a reception strength of at least one synchronization signal block received by using each of the plurality of second receive beams.

2. The electronic device of claim 1 , wherein the processor is configured to transmit, to the base station, information on the determined one synchronization signal block.

3. The electronic device of claim 1 , wherein the processor is configured to determine at least one synchronization signal block of which the reception strength is equal to or greater than a specified threshold value among the plurality of synchronization signal blocks received by using the first receive beam, as the at least one synchronization signal block.

4. The electronic device of claim 3 , wherein the processor is configured to, if a reception strength of each of the plurality of synchronization signal blocks received by using the first receive beam is less than the specified threshold value:
receive the plurality of synchronization signal blocks by using each of the plurality of second receive beams; and
determine one of the plurality of synchronization signal blocks based on the reception strength of each of the plurality of received synchronization signal blocks.

5. The electronic device of claim 1 , wherein the processor is configured to receive the at least one identified synchronization signal block by using each of the plurality of second receive beams, based at least in part on a receive timing of the at least one identified synchronization signal block.

6. The electronic device of claim 5 , wherein the processor is configured to change a state of the processor to a first state or a second state based at least in part on the receive timing, while the at least one identified synchronization signal block is being received by using each of the plurality of second receive beams, and
the processor has higher power consumption in the first state than in the second state.

7. The electronic device of claim 6 , wherein
the processor is configured to transition from the second state to the first state just during a time interval corresponding to the receive timing of the at least one identified synchronization signal block, while the at least one identified synchronization signal block is being received by using each of the plurality of second receive beams.

8. The electronic device of claim 1 , wherein the processor is configured to, after access to the base station, receive the plurality of synchronization signal blocks by using the first receive beam when a specified time elapses after the access to the base station, or when an error rate of communication with the base station is equal to or greater than a specified value.

9. A method for receiving a synchronization signal of an electronic device, comprising:
receiving a plurality of synchronization signal blocks corresponding to a plurality of transmit beams from a base station by using a first receive beam formed using one of a plurality of conductive plates of an antenna array of the electronic device;
identifying at least one of the plurality of synchronization signal blocks received by using the first receive beam based at least on reception strengths of the plurality of synchronization signal blocks;
receiving the at least one identified synchronization signal block by using each of a plurality of second receive beams formed using the plurality of conductive plates; and
determining one synchronization signal block among the at least one identified synchronization signal block based at least on a reception strength of at least one synchronization signal block received using each of the plurality of second receive beams.

10. The method of claim 9 , further comprising transmitting, to the base station, information on the determined one synchronization signal block.

11. The method of claim 9 , wherein the identifying of at least one of the plurality of synchronization signal blocks includes determining at least one synchronization signal block of which the reception strength is equal to or greater than a specified threshold value among the plurality of synchronization signal blocks received by using the first receive beam, as the at least one synchronization signal block.

12. The method of claim 9 , further comprising:
receiving the plurality of synchronization signal blocks by using each of the plurality of second receive beams if the reception strengths of the plurality of synchronization signal blocks received by using the first receive beams is less than a specified threshold value; and
determining one of the plurality of synchronization signal blocks based on the reception strength of each of the plurality of received synchronization signal blocks.

13. The method of claim 9 , wherein the receiving of the at least one identified synchronization signal block includes receiving the at least one identified synchronization signal block by using each of the plurality of second receive beams based at least in part on a receive timing of the at least one identified synchronization signal block.

14. The method of claim 13 , further comprising changing a state of the processor of the electronic device to a first state or a second state based at least in part on the receive timing, while the at least one identified synchronization signal block is being received by using each of the plurality of second receive beams,
wherein the processor has higher power consumption in the first state than in the second state.

15. The method of claim 14 , wherein the changing of the state of the processor of the electronic device to the first state or the second state includes causing the processor to transition from the second state to the first state just during a time interval corresponding to the receive timing of the at least one identified synchronization signal block, while the at least one identified synchronization signal block is being received by using each of the plurality of second receive beams.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Woo Junyoung
• Lee Youngpo
• Lee Hyoungjoo
• Lim Chaiman
• Jung Euichang

Classifications

• H04B7/0696

  Determining beam pairs · CPC title

• H04W56/001 Primary

  Synchronization between nodes · CPC title

• H04B7/088 Primary

  using beam selection · CPC title

• H04B7/0695

  using beam selection · CPC title

• H04B7/0897

  using beamforming per multi-path, e.g. to cope with different directions of arrival [DOA] at different multi-paths · CPC title