Security device generating key based on physically unclonable function and method of operating the same

US11924359B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11924359-B2
Application numberUS-202217973252-A
CountryUS
Kind codeB2
Filing dateOct 25, 2022
Priority dateFeb 12, 2020
Publication dateMar 5, 2024
Grant dateMar 5, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A security device generates a key based on a physically unclonable function (PUF). The security device includes a physically unclonable function (PUF) block, an integrity detector, and a post processor. The PUF block outputs a plurality of first random signals and a plurality of corresponding first inverted random signals each having a logic level opposite to that of each of the plurality of corresponding first random signals. The integrity detector determines data integrity of the plurality of first random signals by using the plurality of first random signals and the plurality of corresponding first inverted random signals. The post processor generates a first row key that includes validity signals satisfying the data integrity.

First claim

Opening claim text (preview).

What is claimed is: 1. A security device comprising: a physically unclonable function (PUF) block comprising a plurality of PUF cells and a validity detector circuit, wherein the plurality of PUF cells are configured to generate a plurality of random signals, and the validity detector circuit is configured to generate a plurality of validity signals based on the plurality of random signals being time-invariant; a non-volatile memory configured to store validity bits and a parity code; and a post processor comprising an enrollment block configured to generate the validity bits based on the plurality of validity signals and configured to: receive the plurality of random signals from the PUF block, read the validity bits and the parity code from the non-volatile memory, select a valid first random signal from the plurality of random signals according to the validity bits, and perform error correction on the first random signal using the parity code to generate a key, wherein the parity code is stored in the non-volatile memory during an enrollment mode and the post processor receives the parity code during a use mode. 2. The security device of claim 1 , wherein the enrollment mode is performed once at a manufacturing point in time when the security device is manufactured. 3. The security device of claim 1 , wherein the use mode is performed at a plurality of points in time at which a key is to be generated by using the security device. 4. The security device of claim 1 , wherein the non-volatile memory is a one-time programmable memory. 5. The security device of claim 1 , wherein a volatile memory is connected between the non-volatile memory and the post processor. 6. The security device of claim 1 , wherein the post processor generates the parity code only once and stores the parity code to nonvolatile memory, and only reads the parity code afterwards. 7. A security device comprising: a physically unclonable function (PUF) block comprising a plurality of PUF cells and a validity detector circuit, wherein the plurality of PUF cells are configured to generate a plurality of random signals, and the validity detector circuit is configured to generate a plurality of validity signals based on the plurality of random signals being time-invariant; a non-volatile memory configured to store validity bits and a parity code; and a post processor comprising an enrollment block configured to generate the validity bits based on the plurality of validity signals and configured to: receive the plurality of random signals from the PUF block, read the validity bits and the parity code from the non-volatile memory, select a first random signal from the plurality of random signals according to the validity bits, and perform error correction on the first random signal using the parity code to generate a key, wherein the validity bits are stored in the non-volatile memory during an enrollment mode and the post processor receives the parity code during a use mode. 8. The security device of claim 7 , wherein the enrollment mode is performed once at a manufacturing point in time when the security device is manufactured. 9. The security device of claim 7 , wherein the use mode is performed at a plurality of points in time at which a key is to be generated by using the security device. 10. The security device of claim 7 , wherein the non-volatile memory is a one-time programmable memory. 11. The security device of claim 7 , wherein a volatile memory is connected between the non-volatile memory and the post processor. 12. The security device of claim 7 , wherein the post processor generates the validity bits only once and stores the validity bits to nonvolatile memory, and only reads the validity bits afterwards.

Assignees

Inventors

Classifications

  • H04L9/3278Primary

    using physically unclonable functions [PUF] · CPC title

  • Protecting data integrity, e.g. using checksums, certificates or signatures · CPC title

  • involving random numbers or seeds · CPC title

  • H04L9/0866Primary

    involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics · CPC title

  • H04L9/0816Primary

    Key establishment, i.e. cryptographic processes or cryptographic protocols whereby a shared secret becomes available to two or more parties, for subsequent use · CPC title

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What does patent US11924359B2 cover?
A security device generates a key based on a physically unclonable function (PUF). The security device includes a physically unclonable function (PUF) block, an integrity detector, and a post processor. The PUF block outputs a plurality of first random signals and a plurality of corresponding first inverted random signals each having a logic level opposite to that of each of the plurality of co…
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification H04L9/3278. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 05 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).