FPGA-based design method and device for equally dividing interval

Patent metadata

Field	Value
Publication number	US-11923863-B2
Application number	US-202017778473-A
Country	US
Kind code	B2
Filing date	Aug 26, 2020
Priority date	Dec 31, 2019
Publication date	Mar 5, 2024
Grant date	Mar 5, 2024

Abstract

Provided is a FPGA-based design method for equally dividing an interval, including the following steps: dividing the oscillation periods of a second pulse signal of a crystal oscillator clock of a FPGA board by the number of equally divided sampling pulses, and obtaining the remainder thereof; dividing the remainder by the number of the equally divided sampling pulses to serve as an error within each sampling interval; using a counter to count from the second pulse, and stopping the counting of the counter once whenever the error within the sampling interval, which is accumulated within the second pulse interval, is greater than or equal to the vibration period. Further provided is a FPGA-based design device for equally dividing an interval. The present application makes full use of the feature of interval equal division calculation, has high precision, and is easy to implement.

First claim

What is claimed is:

1. A Field Programmable Gate Array (FPGA)-based design method for equally dividing an interval, comprising the following steps:
dividing oscillation periods of a second pulse signal of a crystal oscillator clock of a FPGA board by a number of equally divided sampling pulses and obtaining a remainder thereof;
dividing the remainder by the number of the equally divided sampling pulses to serve as an error within each sampling interval; and
using a counter to count from the second pulse signal and stopping counting of the counter whenever the error within the sampling interval, which is accumulated within a second pulse interval, is greater than or equal to the oscillation period.

2. The method according to claim 1 , wherein the step of dividing the oscillation periods of the second pulse signal of the crystal oscillator clock of the FPGA board by the number of the equally divided sampling pulses and obtaining the remainder thereof comprises:
dividing the oscillation periods of the second pulse signal of the crystal oscillator clock of the FPGA board by the number of the equally divided sampling pulses to obtain a quotient thereof; and
generating a sampling pulse within each second pulse interval in response to a value of the counter reaching the quotient while the counter is reset and restarts counting.

3. The method according to claim 2 , further comprising:
performing correction according to a correction formula

Bias
=

n
×

R
N

-
m

,

and stopping counting of the counter within each second pulse interval whenever a value of Bias is greater than or equal to 1, wherein:

R
N

represents an error within each sampling interval, R is the remainder, and N is the number of the equally divided sampling pulses;
n represents a number of sampling pulses and is reset at a next second pulse; and
m represents a number of counting stops of the counter within each second pulse interval, a starting value of m is 0, and a value of m is reset at a next second pulse.

4. The method according to claim 3 , further comprising:
performing correction according to a second correction formula

Bias
=

n
×

R
N

-
m
+

1
2

,

and stopping counting of the counter within each second pulse interval whenever the value of Bias is greater than or equal to 1.

5. The method according to claim 4 , further comprising:
performing correction according to a third correction formula

Bias
′

=

n
×

R
N

-

(

m
+
1

)

+

1
2

=

n
×

R
N

-
k
+

1
2

,

and stopping counting of the counter while incrementing a value of k by 1 within each second pulse interval whenever a value of Bias' is greater than or equal to 0.

6. A Field Programmable Gate Array (FPGA)-based design device for equally dividing an interval, comprising:
one or more processor; and
a memory storing computer-readable instructions executable on the one or more processor, the computer-readable instructions, when executed by the one or more processor, implementing the following steps:
dividing oscillation periods of a second pulse signal of a crystal oscillator clock of a FPGA board by a number of equally divided sampling pulses and obtaining a remainder thereof;
dividing the remainder by the number of the equally divided sampling pulses to serve as an error within each sampling interval; and
using a counter to count from the second pulse signal and stopping counting of the counter whenever the error within the sampling interval, which is accumulated within a second pulse interval, is greater than or equal to the oscillation period.

7. The device according to claim 6 , wherein the step of dividing the oscillation periods of the second pulse signal of the crystal oscillator clock of the FPGA board by the number of the equally divided sampling pulses and obtaining the remainder thereof comprises:
dividing the oscillation periods of the second pulse signal of the crystal oscillator clock of the FPGA board by the number of the equally divided sampling pulses to obtain a quotient thereof; and
generating a sampling pulse within each second pulse interval in response to a value of the counter reaching the quotient while the counter is reset and restarts counting.

8. The device according to claim 7 , wherein the steps further comprise:
performing correction according to a correction formula

Bias
=

n
×

R
N

-
m

,

and stopping counting of the counter within each second pulse interval whenever a value of Bias is greater than or equal to 1, wherein:

R
N

represents an error within each sampling interval, R is the remainder, and N is the number of the equally divided sampling pulses;
n represents a number of sampling pulses and is reset at a next second pulse; and
m represents a number of counting stops of the counter within each second pulse interval, a starting value of m is 0, and a value of m is reset at a next second pulse.

9. The device according

Assignees

• Inspur Suzhou Intelligent Technology Co Ltd

Inventors

• Wang Xiankun

Classifications

• H03L7/191 Primary

  using at least two different signals from the frequency divider or the counter for determining the time difference (H03L7/193, H03L7/195 take precedence) · CPC title

• G06F30/34 Primary

  for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• H03K19/17708

  using an AND matrix followed by an OR matrix, i.e. programmable logic arrays · CPC title

• H03L7/183 Primary

  a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number {(H03L7/1806 takes precedence)} · CPC title

• H03K19/177

  arranged in matrix form · CPC title