Isolated inverters

Patent metadata

Field	Value
Publication number	US-11923787-B2
Application number	US-202217579025-A
Country	US
Kind code	B2
Filing date	Jan 19, 2022
Priority date	Dec 14, 2017
Publication date	Mar 5, 2024
Grant date	Mar 5, 2024

Abstract

An isolated bus inverter system including inverter circuits and a controller. The inverter circuits include a switching array to provide a polyphase alternating current (AC) signal to an output. Each of the inverter circuits includes an energy source isolated from the other inverter circuits of the inverter circuits or a reference isolated from the other inverter circuits of the inverter circuits. The controller is configured to generate timing signals for the inverter circuits to generate the AC signals for the output based on DC signals received from one or more rectifier circuits.

First claim

We claim:

1. An isolated bus inverter system comprising:
a plurality of inverter circuits including a switching array, each inverter circuit of the plurality of inverter circuits configured to provide a respective alternating current (AC) signal to an output, wherein each of the plurality of inverter circuits is connected to a respective energy source isolated on respective input sides of the plurality of inverter circuits from the respective energy sources of the other inverter circuits of the plurality of inverter circuits;
a plurality of rectifier circuits configured to each supply respective direct current (DC) signals to the respective ones of the plurality of inverter circuits, wherein at least one of the plurality of rectifier circuits is connected to one of the plurality of inverter circuits;
a controller configured to generate timing signals for the plurality of inverter circuits to generate the respective AC signals for the output based on the DC signals received from the plurality of rectifier circuits; and
an alternator comprising inductively-coupled windings and configured to provide respective AC power to the plurality of rectifier circuits;
wherein the plurality of rectifier circuits are synchronous rectifier circuits configured to drive the alternator in reverse to transfer power to another one of the plurality of rectifier circuits via the respective windings.

2. The isolated bus inverter system of claim 1 , wherein a first one of the plurality of inverter circuits is configured to provide a first AC signal and a second one of the plurality of inverter circuit is configured to provide a second AC signal.

3. The isolated bus inverter system of claim 1 , further comprising:
a driver circuit configured to magnetically or optically isolate the controller from the plurality of inverter circuits.

4. The isolated bus inverter system of claim 1 , wherein at least one of the energy sources of the plurality of inverter circuits is a fuel cell.

5. The isolated bus inverter system of claim 1 , wherein at least one of the plurality of inverter circuits includes a set of switches for controlling an output for the at least one of the plurality of inverter circuits.

6. The isolated bus inverter system of claim 5 , wherein each of the set of switches is associated with a sensor for measuring an electrical quantity for the set of switches.

7. The isolated bus inverter system of claim 5 , wherein the set of switches includes a positive switch for connecting the output of the at least one of the plurality of inverter circuits to a positive rail and a negative switch for connecting the output of the at least one of the plurality of inverter circuits to a negative rail.

8. The isolated bus inverter system of claim 7 , wherein the controller is configured to generate an anti-shoot through delay period for one of the switches of the set of switches that waits for the anti-shoot through delay period between turning off one of the set of switches and turning on the other of the set of switches.

9. The isolated bus inverter system of claim 8 , wherein the controller monitors characteristics of the set of switches and the anti-shoot through delay period is generated based on the characteristics.

10. The isolated bus inverter system of claim 9 , wherein the controller identifies a shoot through scenario and selects the anti-shoot through delay period in response to the shoot through scenario.

11. The isolated bus inverter system of claim 1 , further comprising:
a filter configured to reduce total harmonic distortion of the output.

12. A method of controlling the isolated bus inverter system of claim 1 to avoid a shoot-through condition, the method comprising:
determining a default time period for waiting between turning off one of at least one pair of switches of at least one of the plurality of inverter circuits and turning on another one of the at least one pair of switches that avoids a shoot-through condition;
monitoring a plurality of electrical parameters of the at least one of the plurality of inverter circuits including a first current through the one of the at least one pair of switches and a second current through the other one of the at least one pair of switches;
identifying a pair of switches of the at least one of the plurality of inverter circuits and associated with a shoot-through condition;
performing a comparison of the electrical parameters including the first current and the second current for the pair of switches associated with the shoot-through condition; and
reducing the default time period until the comparison of the electrical parameters for the pair of switches associated with the shoot-through condition indicates that the shoot-through condition is occurring or there is a risk of the shoot-through condition occurring.

13. The method of claim 12 , further comprising:
incrementally reducing the default time period until a shoot-through trigger is detected for the shoot-through condition.

14. The method of claim 12 , further comprising:
identifying the shoot-through condition from current directions in the electrical parameters.

Assignees

• Kohler Co

Inventors

• Larson Adam
• Frampton Isaac S

Classifications

• H02M7/5387 Primary

  in a bridge configuration · CPC title

• H02M1/38 Primary

  Means for preventing simultaneous conduction of switches · CPC title

• H02M5/4585 Primary

  having a rectifier with controlled elements · CPC title

• H02M7/48

  using discharge tubes with control electrode or semiconductor devices with control electrode · CPC title

• H02M7/5395

  by pulse-width modulation · CPC title