Integrated vertical emitter structure having controlled wavelength
US-2021336422-A1 · Oct 28, 2021 · US
US11923653B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11923653-B2 |
| Application number | US-202117192470-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 4, 2021 |
| Priority date | Dec 23, 2020 |
| Publication date | Mar 5, 2024 |
| Grant date | Mar 5, 2024 |
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In some implementations, an optical device for mounting in a flip-chip configuration includes a plurality of flip-chip bumps that are arranged in a pattern on the optical device, wherein the pattern is not aligned with a crystal cleavage plane associated with a substrate of the optical device. In some implementations, the optical device further includes a gap that separates a primary region of the optical device and a secondary region of the optical device, wherein at least one portion of a side of the gap is oriented at a non-zero angle to the crystal cleavage plane.
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What is claimed is: 1. An optical device for mounting in a flip-chip configuration, comprising: a primary region; a secondary region; and a gap that separates the primary region and the secondary region, wherein: a first portion of a side of the gap is oriented at a first non-zero angle to a crystal cleavage plane associated with a substrate of the optical device, a second portion of the side of the gap is oriented at a second non-zero angle to the crystal cleavage plane, the first non-zero angle is different from the second non-zero angle, and more than two portions of the side of the gap intersect the crystal cleavage plane. 2. The optical device of claim 1 , wherein the first non-zero angle is within a range of 5 to 15 degrees. 3. The optical device of claim 1 , further comprising a plurality of flip-chip bumps that are arranged in a pattern on at least one of the primary region and the secondary region. 4. The optical device of claim 1 , wherein the optical device is a vertical-cavity surface-emitting laser (VCSEL) optical device. 5. The optical device of claim 1 , wherein the primary region is associated with an anode associated with the optical device and the secondary region is associated with a cathode associated with the optical device. 6. The optical device of claim 1 , wherein the orientation of the first portion of the side of the gap causes an amount of mechanical stress along the crystal cleavage plane to satisfy a mechanical stress breakage threshold, wherein the amount of mechanical stress is created by attachment of the primary region and the secondary region to a component of another device. 7. The optical device of claim 1 , wherein the gap extends from within a threshold distance of a first side of the optical device to within the threshold distance of a second side of the optical device. 8. The optical device of claim 3 , wherein the pattern is not aligned with the crystal cleavage plane. 9. The optical device of claim 3 , wherein the pattern comprises multiple rows of flip-chip bumps, wherein adjacent rows, of the multiple rows, are laterally offset from each other. 10. The optical device of claim 3 , wherein the pattern is a non-uniform pattern. 11. The optical device of claim 1 , wherein the second non-zero angle is within a range of 5 to 15 degrees. 12. The optical device of claim 1 , wherein the side of the gap has a sinusoidal shape. 13. A wafer, comprising: a plurality of chips that include a plurality of gaps; and a crystal cleavage plane associated with the wafer, wherein: a first portion of a side of a gap of the plurality of gaps is oriented at a first non-zero angle to the crystal cleavage plane, a second portion of the side of the gap is oriented at a second non-zero angle to the crystal cleavage plane, the first non-zero angle is different from the second non-zero angle, and more than two portions of the side of the gap intersect the crystal cleavage plane. 14. The wafer of claim 13 , wherein the plurality of chips include a plurality of chip bumps, wherein: the plurality of chip bumps are arranged in a pattern on the plurality of chips. 15. The wafer of claim 14 , wherein the pattern of chip bumps is a result of a rotation, relative to the wafer, of a mask used to manufacture the plurality of chip bumps. 16. The wafer of claim 14 , wherein the pattern comprises a non-uniform pattern of chip bumps. 17. The wafer of claim 14 , wherein the pattern comprises multiple rows of chip bumps, wherein adjacent rows, of the multiple rows, are laterally offset from each other. 18. The wafer of claim 14 , wherein the pattern comprises a uniform pattern of chip bumps. 19. The wafer of claim 13 , wherein the side of the gap has a sinusoidal shape. 20. The wafer of claim 13 , wherein at least one of the first non-zero angle or the second non-zero angle is within a range of 5 to 15 degrees. 21. The wafer of claim 13 , wherein the plurality of chips are vertical-cavity surface-emitting laser (VCSEL) chips. 22. The wafer of claim 13 , wherein the orientation of the first portion of the side of the gap causes an amount of mechanical stress along the crystal cleavage plane to satisfy a mechanical stress breakage threshold.
Up-side down mountings, e.g. Flip-chip, epi-side down mountings or junction down mountings · CPC title
having a vertical cavity · CPC title
having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL] · CPC title
Lead-frames · CPC title
Wire-bonding · CPC title
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