Semiconductor device package with die cavity substrate

Patent metadata

Field	Value
Publication number	US-11923258-B2
Application number	US-202117469480-A
Country	US
Kind code	B2
Filing date	Sep 8, 2021
Priority date	Dec 10, 2020
Publication date	Mar 5, 2024
Grant date	Mar 5, 2024

Abstract

An example includes: a substrate having a first package surface, having a second package surface opposite the first package surface, and having a die cavity with a depth extending into the first package surface; a semiconductor die having bond pads on a first die surface and having a second die surface opposite the first die surface, the semiconductor die having a die thickness, the second die surface of the semiconductor die mounted in the die cavity; a cover over a portion of the first die surface; conductors coupling the bond pads of the semiconductor die to bond fingers on the first package surface of the substrate; and dielectric material over the conductors, the bond fingers, the bond pads, at least a portion of the first semiconductor die and at least a portion of the cover, wherein the dielectric material extends above the first package surface of the substrate.

First claim

What is claimed is:

1. An apparatus, comprising:
a substrate having a substrate surface, a cavity extending into the substrate surface, and a trench extending into the substrate surface, the trench spaced from the cavity;
a die having bond pads on a first die surface and having a second die surface opposite the first die surface, the second die surface of the die in the cavity;
a cover over at least a portion of the first die surface of the die;
conductors coupling the bond pads of the die to conductive material on the substrate surface, the conductors between the cavity and the trench; and
dielectric material over the conductors, wherein the dielectric material extends from the die to an edge of the trench.

2. The apparatus of claim 1 , wherein the trench is a first trench parallel to a first end of the cavity, the substrate surface of the substrate further having a second trench parallel to a second end of the cavity, the conductive material on the substrate surface between the cavity and the first trench and between the cavity and the second trench.

3. The apparatus of claim 1 , wherein the conductors are bond wires connected between the bond pads on the die and the conductive material on the substrate surface of the substrate.

4. The apparatus of claim 3 , wherein the bond wires comprise gold, copper, palladium coated copper, silver, or aluminum.

5. The apparatus of claim 1 , wherein the conductors are bond wires or ribbon bonds.

6. The apparatus of claim 1 , wherein the cover comprises an optically transmissive window.

7. The apparatus of claim 6 , wherein the cover is glass.

8. The apparatus of claim 1 , wherein the die comprises a digital micromirror device (DMD).

9. The apparatus of claim 1 , wherein the dielectric material comprises a mold compound.

10. The apparatus of claim 9 , wherein the mold compound comprises a thermoset epoxy resin.

11. The apparatus of claim 1 , wherein the dielectric material comprises a glob top material.

12. A packaged semiconductor device, comprising:
a substrate having a substrate surface, the substrate having a cavity extending into the substrate surface, and the substrate having a trench spaced from the cavity and extending into the substrate surface;
a die having a first surface and a second surface opposite the first surface, the die having bond pads on the first surface, the second surface in the cavity;
a cover over at least a portion of the first surface of the die;
conductors coupling the bond pads on the first surface of the die to conductive material on the substrate surface, the conductive material between the trench and the cavity; and
dielectric material over the conductors and over the substrate surface from the die to an edge of the trench, the dielectric material having an upper surface that is above the substrate surface.

13. The packaged semiconductor device of claim 12 , wherein the die comprises a spatial light modulator, a light emitting diode (LED) or laser diode, an imager, a photosensor, or a micro electro-mechanical system (MEMS) device.

14. The packaged semiconductor device of claim 12 , wherein the die comprises a digital micromirror device (DMD).

15. The packaged semiconductor device of claim 14 , wherein the dielectric material comprises a glob top dielectric material that is liquid or gel at room temperature.

16. The packaged semiconductor device of claim 12 , wherein the substrate is a ceramic substrate.

17. The packaged semiconductor device of claim 12 , wherein the substrate is a flame-retardant 4 (FR4) substrate or a bismaleimide triazine (BT) substrate.

18. An apparatus, comprising:
a substrate having a substrate surface, the substrate having a cavity extending into the substrate surface, trenches extending into the substrate surface, the trenches spaced from the cavity;
a die comprising a spatial light modulator, the die having an active surface and a backside surface opposite the active surface, the die having bond pads on the active surface and having the backside surface mounted in the cavity;
an optically transmissive window mounted over at least a portion of the active surface of the die;
bond wires coupling the bond pads to conductive material on the substrate surface, the conductive material spaced from the cavity, the conductive material on the substrate surface between the cavity and the trenches; and
dielectric material over the bond wires, the conductive material, and the bond pads, the dielectric material extending from the die to an edge of one of the trenches.

19. The apparatus of claim 18 , wherein a thickness of the die is equal to a depth of the cavity.

20. The apparatus of claim 18 , wherein a thickness of the die is less than a depth of the cavity.

Assignees

• Texas Instruments Inc

Inventors

• Morrison William Robert
• Haskett Bradley Morgan

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/5525

  comprising copper [Cu] · CPC title

• H10W72/5524

  comprising aluminium [Al] · CPC title

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W72/555

  of outermost layers of multilayered bond wires, e.g. material of a coating · CPC title