Integrated circuit structure

Patent metadata

Field	Value
Publication number	US-11923253-B2
Application number	US-202318167442-A
Country	US
Kind code	B2
Filing date	Feb 10, 2023
Priority date	Apr 24, 2017
Publication date	Mar 5, 2024
Grant date	Mar 5, 2024

Abstract

A device includes a first transistor, a second transistor, and a dielectric structure. The first transistor is over a substrate and has a first gate structure. The second transistor is over the substrate and has a second gate structure. The dielectric structure is between the first gate structure and the second gate structure. The dielectric structure has a width increasing from a bottom position of the dielectric structure to a first position higher than the bottom position of the dielectric structure. A width of the first gate structure is less than the width of the dielectric structure at the first position.

First claim

What is claimed is:

1. A device, comprising:
a semiconductor fin disposed extending from a semiconductor substrate;
a first transistor having a first gate structure over the semiconductor fin;
a second transistor having a second gate structure over the semiconductor fin; and
a dielectric structure between the first gate structure and the second gate structure,
wherein the dielectric structure extends to at least a level of a top surface of the first gate structure and a top surface of the second gate structure; and
wherein the dielectric structure has a width increasing from a bottom position of the dielectric structure in the semiconductor fin to a first position higher than the bottom position of the dielectric structure and in the semiconductor fin, and wherein a width of the first gate structure is less than the width of the dielectric structure in the semiconductor fin at the first position.

2. The device of claim 1 , wherein the dielectric structure has a first slope from the bottom position to the first position, and a second slope from the first position to a second position higher than the first position, and the second slope is different from the first slope.

3. The device of claim 1 , wherein the dielectric structure comprises more than one material.

4. The device of claim 1 , wherein the dielectric structure at the first position interfaces a material of the semiconductor substrate.

5. The device of claim 1 , wherein the dielectric structure is spaced apart from the first gate structure of the first transistor by a first distance, and spaced apart from a source/drain region of the first transistor by a second distance, and wherein the second distance is smaller than the first distance.

6. The device of claim 1 , wherein the dielectric structure is spaced apart from source/drain regions of the first transistor and source/drain regions of the second transistor.

7. A device, comprising:
a first transistor over a semiconductor fin, the semiconductor fin extending upwards from a substrate;
a second transistor over the semiconductor fin; and
an isolation structure isolating the first transistor from the second transistor, the isolation structure having:
a lower dielectric portion in the semiconductor fin and lower than tops of source/drain regions of the first and second transistors; and
an upper dielectric portion above the semiconductor fin and higher than the tops of the source/drain regions of the first and second transistors, wherein a sidewall of the lower dielectric portion in the semiconductor fin has more slope change than a sidewall of the upper dielectric portion above the semiconductor fin, and the upper dielectric portion has a width greater than a minimal width of the lower dielectric portion.

8. The device of claim 7 , wherein the sidewall of the lower dielectric portion has two or more slope changes.

9. The device of claim 7 , wherein the isolation structure comprises more than one material.

10. The device of claim 7 , wherein a bottom position of the isolation structure is lower than a bottom of a shallow trench isolation (STI) region in the substrate.

11. The device of claim 7 , wherein the lower dielectric portion comprises has a width increasing from a bottom of the lower dielectric portion to a first position higher than the bottom of the lower dielectric portion, and wherein a width of a first gate structure of the first transistor is less than the width of the lower dielectric portion at the first position, and wherein in a cross-sectional view, a top surface of the isolation structure is not covered by any gate structures.

12. A device, comprising:
a first transistor formed on a first region of a semiconductor fin;
a second transistor formed on a second region of the semiconductor fin; and
a dielectric structure isolating the first transistor from the second transistor, wherein the dielectric structure is spaced apart from source/drain regions of the first transistor and source/drain regions of the second transistor, and the dielectric structure comprises a non-linear sidewall profile, the non-linear sidewall profile comprises a bottom sidewall, a first sidewall above the bottom sidewall, and a second sidewall above the first sidewall, wherein the bottom sidewall and the first sidewall are each disposed in the semiconductor fin, wherein the bottom sidewall is tilted from a direction normal to a substrate by a first angle, the first sidewall and the bottom sidewall form an included angle greater than the first angle, and the second sidewall is non-parallel with the bottom sidewall and the first sidewall.

13. The device of claim 12 , wherein the bottom sidewall of the dielectric structure interfaces the substrate.

14. The device of claim 12 , wherein the first sidewall of the dielectric structure interfaces the substrate.

15. The device of claim 12 , wherein the second sidewall of the dielectric structure extends along the direction normal to the substrate.

16. The device of claim 12 , wherein the second sidewall of the dielectric structure is above a top position of the substrate.

17. The device of claim 12 , wherein the dielectric structure comprises more than one material.

18. The device of claim 12 , wherein the bottom sidewall of the dielectric structure is lower than a bottom of a shallow trench isolation (STI) region in the substrate.

19. The device of claim 12 , wherein the first angle is an obtuse angle.

20. The device of claim 12 , wherein the first angle and the included angle are each measured from above the bottom sidewall.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Kuei-Ming
• Hsieh Rei-Jay
• Wu Cheng-Han
• Lin Chie-Luan

Classifications

• H10W10/0145 Primary

  of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence) · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/0151

  Manufacturing their isolation regions · CPC title