Adaptive block mapping

Patent metadata

Field	Value
Publication number	US-11922069-B2
Application number	US-202217750131-A
Country	US
Kind code	B2
Filing date	May 20, 2022
Priority date	May 20, 2022
Publication date	Mar 5, 2024
Grant date	Mar 5, 2024

Abstract

Methods, systems, and devices for adaptive block mapping are described. In some examples, a first superblock and a second superblock may be established across one or more dice of a memory device. The superblocks may each include one or more blocks from a plurality of planes of a memory die. In some examples, the second superblock may include at least one bad block (e.g., defective block) in addition to one or more good blocks (e.g., non-defective blocks). The memory device may receive a command for writing data in a first mode and may write a first subset of the data to the first superblock in the first mode, a second subset of the data to the second superblock in the first mode, and one or more blocks associated with the second superblock in a second mode. Additionally or alternatively, the memory device may receive a second command for writing data in the second mode and may write the data to the first superblock in the first mode.

First claim

What is claimed is:

1. An apparatus, comprising:
a memory comprising a plurality of planes that each comprise a plurality of blocks, wherein each block of the plurality of blocks includes a plurality of non-volatile memory cells; and
a controller coupled with the memory and operable to:
identify a first set of blocks of the memory and a second set of blocks of the memory, wherein the second set of blocks is associated with the first set of blocks;
receive, from a host device, one or more commands for writing data to the memory in a first mode;
write, in the first mode, a first portion of the data to blocks of the first set of blocks and a second portion of the data to a first subset of blocks of the second set of blocks based at least in part on receiving the one or more commands from the host device, wherein the first mode comprises writing a plurality of bits of data per memory cell; and
write, in a second mode, a third portion of the data to a second subset of blocks of the second set of blocks based at least in part on receiving the one or more commands from the host device, wherein the second mode comprises writing one bit of data per memory cell.

2. The apparatus of claim 1 , wherein the controller is operable to:
receive, from the host device, a second set of one or more commands for writing second data to the memory in the second mode; and
write, in the second mode, the second data to the blocks of the first set of blocks based at least in part on receiving the second set of one or more commands from the host device.

3. The apparatus of claim 2 , wherein the controller is operable to:
refrain from writing, in the second mode, the second data to the second set of blocks based at least in part on receiving the second set of one or more commands from the host device.

4. The apparatus of claim 1 , wherein at least one block of the memory is a defective block, wherein the data is written to the second subset of blocks of the second set of blocks of the memory based at least in part on the at least one block being defective.

5. The apparatus of claim 4 , wherein the second subset of blocks of the second set of blocks are in different planes of the memory than the at least one block that is defective.

6. The apparatus of claim 1 , wherein each of the first subset of blocks of the second set of blocks is a corresponding block from different planes of the memory.

7. An apparatus, comprising:
a memory comprising a plurality of planes that each comprise a plurality of blocks, wherein each block of the plurality of blocks includes a plurality of non-volatile memory cells; and
a controller coupled with the memory and operable to:
identify a first set of blocks of the memory and a second set of blocks of the memory, wherein the second set of blocks is associated with the first set of blocks;
receive, from a host device, one or more commands for writing data to the memory in a first mode;
write, in the first mode, a first portion of the data to blocks of the first set of blocks and a second portion of the data to a first subset of blocks of the second set of blocks based at least in part on receiving the one or more commands from the host device; and
write, in a second mode, a third portion of the data to a second subset of blocks of the second set of blocks based at least in part on receiving the one or more commands from the host device, wherein a quantity of blocks included in the first subset of blocks of the second set of blocks and the second subset of blocks of the second set of blocks of the memory is greater than a quantity of blocks included in the first set of blocks.

8. An apparatus, comprising:
a memory comprising a plurality of planes that each comprise a plurality of blocks, wherein each block of the plurality of blocks includes a plurality of non-volatile memory cells; and
a controller coupled with the memory and operable to:
receive, from a host device, a first command for writing first data to the memory in a first mode;
write, in the first mode, a first portion of the first data to at least a first block of a first set of blocks of the memory based at least in part on receiving the first command from the host device and a first cursor value associated with the first mode indicating the first set of blocks, wherein the first mode comprises writing a plurality of bits of data per memory cell;
write, in a second mode, a second portion of the first data to at least a second block of the first set of blocks based at least in part on receiving the first command from the host device, wherein the second mode comprises writing one bit of data per memory cell;
receive, from the host device, a second command for writing second data to the memory in the second mode, wherein upon receiving the second command a second cursor value associated with the second mode indicates the first set of blocks; and
write, in the second mode, the second data to one or more blocks of a second set of blocks of the memory based at least in part on receiving the second command from the host device and the second cursor value associated with the second mode indicating the first set of blocks.

9. The apparatus of claim 8 , wherein the controller is operable to:
refrain from writing the second data to blocks of the first set of blocks based at least in part on receiving the second command for writing the second data to the memory and the second cursor value associated with the second mode indicating the first set of blocks.

10. The apparatus of claim 8 , wherein the controller is operable to:
identify at least the second block of the first set of blocks of the memory based at least in part on a third block of the memory being defective, wherein the controller is operable to write the second portion of the first data to at least the second block in the second mode based at least in part on identifying at least the second block of the memory.

11. The apparatus of claim 10 , wherein the second block of the memory is in a different plane of the memory than the third block of the memory.

12. The apparatus of claim 8 , wherein the first set of blocks is associated with a third set of blocks when data is written to the memory in the first mode.

13. The apparatus of claim 12 , wherein the first set of blocks includes a larger quantity of blocks of the memory than the third set of blocks.

14. The apparatus of claim 8 , wherein the first command comprises one or more logical addresses for writing the first data to the first set of blocks in the first mode.

15. An apparatus, comprising:
a memory comprising a plurality of planes that each comprise a plurality of blocks, wherein each block of the plurality of blocks includes a plurality of non-volatile memory cells; and
a controller coupled with the memory and operable to:
receive, from a host device, a first command for writing first data to the memory in a first mode;
write, in the first mode, a first portion of the first data to at least a first block of a first set of blocks of the memory based at least in part on receiving the first command from the host device and a first cursor value associated with the first mode indicating the first set of blocks, wherein the first set of blocks is associated with a third set of blocks when data is written to the memory in the first mode, and wherein, to write the first data in the first mode, the controller is operable to write, in the first mode, a third portion of the first data to at least a fourth block of the third set of blocks prior to writing the first portion of the first data to the at least the first block of the first

Assignees

• Micron Technology Inc

Inventors

• Sassara Alberto
• D'Eliseo Giuseppe
• Drissi Lalla Fatima
• Esposito Luigi
• Papa Paolo
• Del Prete Salvatore
• Luo Xiangang
• Zhu Xiaolai

Classifications

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• G06F3/0679 Primary

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/064

  Management of blocks · CPC title