Stack register having different ferroelectric memory element constructions

Patent metadata

Field	Value
Publication number	US-11922055-B2
Application number	US-202217730345-A
Country	US
Kind code	B2
Filing date	Apr 27, 2022
Priority date	Apr 28, 2021
Publication date	Mar 5, 2024
Grant date	Mar 5, 2024

Abstract

Apparatus and method for managing data in a processing system, such as but not limited to a data storage device such as a solid-state drive (SSD). A ferroelectric stack register memory has a first arrangement of ferroelectric memory cells (FMEs) of a first construction and a second arrangement of FMEs of a different, second construction arranged to provide respective cache lines for use by a controller, such as a programmable processor. A pointer mechanism is configured to provide pointers to point to each of the respective cache lines based on a time sequence of operation of the processor. Data sets can be migrated to the different arrangements by the controller as required based on the different operational characteristics of the respective FME constructions. The FMEs may be non-volatile and read-destructive. Refresh circuitry can be selectively enacted under different operational modes.

First claim

What is claimed is:

1. A ferroelectric stack register memory comprising:
a first arrangement of ferroelectric memory cells (FMEs) having a first construction arranged to provide a first number of cache lines adapted to respectively receive a corresponding first number of data entries from a processor;
a second arrangement of FMEs having a different, second construction arranged to provide a second number of cache lines adapted to respectively receive a corresponding second number of data entries from the processor; and
a pointer mechanism configured to provide pointers to point to each of the respective first and second numbers of cache lines based on a time sequence of operation of the processor.

2. The memory of claim 1 , wherein the first number of cache lines are formed of ferroelectric tunneling junction (FJT) memory cells.

3. The memory of claim 1 , wherein the first number of cache lines are formed as ferroelectric random access memory (FeRAM) memory cells each having at least one transistor and at least one capacitor.

4. The memory of claim 3 , wherein the at least one capacitor in each FeRAM memory cell has a ferroelectric layer.

5. The memory of claim 1 , wherein the first number of cache lines are formed as ferroelectric field effect transistors (FeFETs).

6. The memory of claim 1 , wherein the stack register is arranged as a plurality of ferroelectric layers separated by intervening non-ferroelectric layers arranged as a stack having an input end and an output end, and wherein a read/write advancement circuit is adapted to stepwise advance data bits to each of the ferroelectric layers from the input end to the output end to populate the stack.

7. The memory of claim 1 , wherein the processor selects between the first and second sets of cache lines responsive to a type of data to be stored to the stack register.

8. The memory of claim 1 , wherein the stack register forms a portion of a data storage device having a main non-volatile memory (NVM) to store user data from a client device.

9. The memory of claim 8 , wherein the data storage device is a solid-state drive (SSD) in which the NVM is a flash memory.

10. The memory of claim 1 , wherein the processor is characterized as a programmable processor which executes program instructions from a memory, and at least some of the program instructions are stored in the stack register prior to said execution thereof.

11. A data storage device, comprising:
a non-volatile memory (NVM) characterized as a main memory store for user data accessible by an external client device;
a controller configured to transfer the user data between the NVM and the external client device responsive to commands issued by the external client device; and
a local memory configured for use by the controller to support said transfers of the user data, the local memory characterized as a ferroelectric stack register memory comprising a first arrangement of ferroelectric memory cells (FMEs) having a first construction, a second arrangement of FMEs having a different, second construction, and a pointer mechanism configured to provide pointers to point to cache lines associated with each of the first and second arrangements of FMEs responsive to inputs supplied by the controller.

12. The data storage device of claim 11 , wherein the NVM comprises at least a selected one of flash memory or rotatable magnetic recording media.

13. The data storage device of claim 11 , wherein the controller comprises a programmable processor configured to execute program instructions stored in the stack register.

14. The data storage device of claim 11 , wherein the local memory further comprises read/write circuitry configured to read data from and write data to the stack register, and refresh circuitry configured to selectively refresh data to the stack register after a read operation responsive to a mode selection input from the controller.

15. The data storage device of claim 11 , wherein each of the first and second constructions are selected from FTJs, FeRAMs or FeFETs.

16. The data storage device of claim 11 , wherein the controller stores a selected data set in the first arrangement of FMEs and subsequently transfers the selected data set to the second arrangement of FMEs.

17. A method comprising:
initiating communication between a controller and a ferroelectric stack register memory having a first arrangement of ferroelectric memory cells (FMEs) having a first construction arranged to provide a first number of cache lines adapted to respectively receive a corresponding first number of data entries from the processor and a second arrangement of FMEs having a different, second construction arranged to provide a second number of cache lines adapted to respectively receive a corresponding second number of data entries from the processor;
using the controller to store a first data set to the first number of cache lines of the first arrangement and a second data set to the second number of cache lines of the second arrangement; and
utilizing a pointer mechanism to provide pointers to point to each of the respective first and second numbers of cache lines based on a time sequence of operation of the controller.

18. The method of claim 17 , further comprising using the controller to migrate the first data set to the second number of cache lines of the second arrangement and updating the pointer mechanism to reflect said migration.

19. The method of claim 17 , wherein each of the first and second constructions are selected from different ones of FTJs, FeRAMs or FeFETs.

20. The method of claim 17 , wherein the stack register forms a portion of a data storage device having a main non-volatile memory (NVM) to store user data from a client device.

Assignees

• Seagate Technology Llc

Inventors

• Trantham Jon D
• Viraraghavan Praveen
• Dykes John W
• Gilbert Ian J
• Kalarickal Sangita Shreedharan
• Totin Matthew J
• El-Batal Mohamad
• Mehta Darshana H

Classifications

• G06F3/0655 Primary

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G11C11/22

  using ferroelectric elements · CPC title

• G06F12/0875 Primary

  with dedicated cache, e.g. instruction or stack · CPC title