Semiconductor structure and method of forming the same

Patent metadata

Field	Value
Publication number	US-11921318-B2
Application number	US-202217742974-A
Country	US
Kind code	B2
Filing date	May 12, 2022
Priority date	May 13, 2021
Publication date	Mar 5, 2024
Grant date	Mar 5, 2024

Abstract

A method of forming a semiconductor structure includes: providing an initial substrate having a first region and a second region; forming a first substrate on the initial substrate; forming a first insulating layer on the first substrate; forming a second substrate on the first insulating layer; removing the second substrate in the second region to form a second insulating layer on the first insulating layer in the second region; and forming a plurality of passive devices on the second insulating layer in the second region and forming a plurality of active devices on the second substrate in the first region.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a substrate having a first region and a second region;
a first insulating layer on the substrate;
a second insulating layer on the first insulating layer in the second region;
a plurality of active devices on the first insulating layer in the first region;
a plurality of passive devices on the second insulating layer;
a third insulating layer on the plurality of passive devices;
a fourth insulating layer on the plurality of active devices, a top surface of the fourth insulating layer being leveled with a top surface of the third insulating layer; and
a fifth insulating layer on the third insulating layer and the fourth insulating layer.

2. The semiconductor structure according to claim 1 , further comprising:
a grating layer in the third insulating layer.

3. The semiconductor structure according to claim 1 , further comprising:
an electrical interconnection structure connecting to an active device of the plurality active devices.

4. The semiconductor structure according to claim 1 , further comprising:
a passivation layer on the fifth insulating layer;
a first light inlet passing through the passivation layer and over the plurality of active devices; and
a second light inlet passing through each of the passivation layer, the fifth insulating layer, and the third insulating layer, and over the plurality of passive devices.

5. The semiconductor structure according to claim 1 , wherein:
the plurality of passive devices are made of a material based on silicon nitride; and/or
the plurality of active devices are made of a material based on silicon.

6. The semiconductor structure according to claim 1 , wherein:
the plurality of active devices include at least one of a modulator or a detector; and/or
the plurality of passive devices include a waveguide device.

7. A method of forming a semiconductor structure, comprising:
providing an initial substrate having a first region and a second region;
forming a first substrate on the initial substrate;
forming a first insulating layer on the first substrate;
forming a second substrate on the first insulating layer;
removing the second substrate in the second region to form a second insulating layer on the first insulating layer in the second region; and
forming a plurality of passive devices on the second insulating layer in the second region and forming a plurality of active devices on the second substrate in the first region.

8. The method of forming the semiconductor structure according to claim 7 , wherein forming the plurality of passive devices includes:
forming a passive device material layer on the second insulating layer;
performing a first patterning process on the passive device material layer for multiple times to form a plurality of initial passive devices; and
performing an annealing process on the plurality of initial passive devices to form the plurality of passive devices, wherein an annealing temperature in the annealing process is higher than 1000° C.

9. The method of forming the semiconductor structure according to claim 8 , wherein:
the plurality of passive devices are made of a material based on silicon nitride; and/or
the second substrate are made of a material based on silicon.

10. The method of forming the semiconductor structure according to claim 7 , wherein:
the plurality of active devices include at least one of a modulator or a detector.

11. The method of forming the semiconductor structure according to claim 8 , wherein forming the plurality of active devices includes:
forming a plurality of device structures in the first region; and
performing an ion injection process in the first region for multiple times.

12. The method of forming the semiconductor structure according to claim 11 , wherein:
the plurality of device structures include at least one of a gate structure or an epitaxial layer in the second substrate.

13. The method of forming the semiconductor structure according to claim 11 , further comprising while forming the plurality of initial passive devices:
forming a plurality of barrier layers on the plurality of device structures.

14. The method of forming the semiconductor structure according to claim 11 , wherein the ion injection process includes:
forming a third insulating layer on the plurality of passive devices and the plurality of barrier layers;
removing a portion of the third insulating layer and the plurality of barrier layers to form a processing opening in the third insulating layer, the processing opening being over the plurality of device structures; and
injecting ions into the plurality of device structures to form the plurality of active devices.

15. The method of forming the semiconductor structure according to claim 14 , wherein:
the third insulating layer includes a grating layer.

16. The method of forming the semiconductor structure according to claim 15 , further comprising after the plurality of active devices are formed:
forming an electrical interconnection structure over the plurality of active devices.

17. The method of forming the semiconductor structure according to claim 16 , further comprising after the plurality of active devices are formed:
forming a fourth insulating layer on the plurality of active devices, a top surface of the fourth insulating layer being leveled with a top surface of the third insulating layer; and
forming a fifth insulating layer on the third insulating layer and the fourth insulating layer, the electrical interconnection structure being in the fourth insulating layer and the fifth insulating layer.

18. The method of forming the semiconductor structure according to claim 17 , further comprising after the plurality of active devices are formed:
forming a passivation layer on the fifth insulating layer;
forming a first light inlet passing through the passivation layer, the first light inlet being over the plurality of active devices; and
forming a second light inlet passing through the passivation layer, the fifth insulating layer, and the third insulating layer, the second light inlet being over the plurality of passive devices.

19. The method of forming the semiconductor structure according to claim 18 , wherein forming the second light inlet includes:
removing a portion of the passivation layer, the fifth insulating layer, the third insulating layer to form the second light inlet.

Assignees

• Semiconductor Mfg Int Shanghai Corp
• Semiconductor Mfg Int Beijing Corp

Inventors

• Chen Xiaojun
• Zeng Honglin
• Feng Xia
• Zhang Dongsheng
• Yin Xiage
• Wu Jiaheng

Classifications

• H10D30/6741

  Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755) · CPC title

• H10D30/0323

  comprising monocrystalline silicon · CPC title

• H10D86/201

  the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence) · CPC title

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/021

  of multiple TFTs · CPC title