Double-sided capacitor structures and forming methods thereof

Patent metadata

Field	Value
Publication number	US-11916102-B2
Application number	US-202117310899-A
Country	US
Kind code	B2
Filing date	Mar 8, 2021
Priority date	Mar 20, 2020
Publication date	Feb 27, 2024
Grant date	Feb 27, 2024

Abstract

A method for forming a double-sided capacitor structure includes: providing a base, the base including a substrate, a plurality of capacitor contacts located in the substrate, a stack structure located on a surface of the substrate and a plurality of capacitor holes running through the stack structure and exposing the capacitor contacts, the stack structure including sacrificial layers and support layers which are stacked alternately; successively forming a first electrode layer, a first dielectric layer and a second electrode layer on inner walls of the capacitor holes; forming a first conductive filling layer in the capacitor holes; forming an auxiliary layer for sealing the capacitor holes; removing a part of the auxiliary layers and several of the support layers and the sacrificial layers to expose the first electrode layer; and, forming a second dielectric layer and a third electrode layer.

First claim

What is claimed is:

1. A method for forming a double-sided capacitor structure, comprising:
providing a base, the base comprising a substrate, a plurality of capacitor contacts located in the substrate, a stack structure located on a surface of the substrate and a plurality of capacitor holes running through the stack structure and exposing the capacitor contacts, the stack structure comprising sacrificial layers and support layers, the sacrificial layers and the support layers stacked alternately in a direction perpendicular to the substrate;
successively forming, on inner walls of the capacitor holes, a first electrode layer, a first dielectric layer and a second electrode layer stacked along a radial direction of the capacitor holes;
filling a first conductive material in the capacitor holes to form a first conductive filling layer;
forming an auxiliary layer for sealing the capacitor holes;
removing a part of the auxiliary layer and several of the support layers and the sacrificial layers to expose the first electrode layer, a remaining of the auxiliary layer being divided into a plurality of sub-auxiliary layers, each of the sub-auxiliary layers being at least overlapped with two capacitor holes; and
forming a second dielectric layer covering a surface of the first electrode layer and surfaces of the sub-auxiliary layers and a third electrode layer covering a surface of the second dielectric layer to form a double-sided capacitor structure.

2. The method according to claim 1 , wherein the first electrode layer, the first dielectric layer and the second electrode layer are also successively stacked on a top surface of the stack structure, and the forming a first conductive filling layer comprises:
depositing the first conductive material in the capacitor holes and on a surface of the second electrode layer located on the top surface of the stack structure; and
removing the first conductive material covering the surface of the second electrode layer on the top surface of the stack structure.

3. The method according to claim 2 , wherein the forming an auxiliary layer for sealing the capacitor holes comprises:
removing the first electrode layer, the first dielectric layer and the second electrode layer covering the top surface of the stack structure; and
forming an auxiliary layer covering the second electrode layer on the top surface of the stack structure and sealing the capacitor holes.

4. The method according to claim 1 , wherein the stack structure comprises a first support layer, a first sacrificial layer, a second support layer, a second sacrificial layer and a third support layer successively stacked along a direction perpendicular to the substrate; and, the removing a part of the auxiliary layer and several of the support layers and the sacrificial layers comprises:
forming a photoresist layer covering the auxiliary layer, the photoresist layer having an etching window for exposing the auxiliary layer; and
successively etching the auxiliary layer, the third support layer, the second sacrificial layer, the second support layer and the first sacrificial layer along the etching window, so that a remaining of the auxiliary layer is divided into a plurality of sub-auxiliary layers, each of the sub-auxiliary layers being overlapped with two capacitor holes.

5. The method according to claim 1 , wherein a material of the auxiliary layer is the same as a material of the support layers.

6. The method according to claim 1 , after forming a double-sided capacitor structure, the method further comprises:
depositing a second conductive material on a surface of the third electrode layer to form a second conductive filling layer.

7. A double-sided capacitor structure, comprising:
a base, the base comprising a substrate, a plurality of capacitor contacts located in the substrate, a stack structure located on a surface of the substrate and a plurality of capacitor holes running through the stack structure and exposing the capacitor contacts, the stack structure at least comprising a plurality of support layers stacked along a direction perpendicular to the substrate;
a first electrode layer, covering inner walls of the capacitor holes;
a first dielectric layer, covering sidewall surfaces and bottom wall surfaces of the first electrode layer facing the capacitor holes;
a second electrode layer, covering sidewall surfaces and bottom wall surfaces of the first dielectric layer facing the capacitor holes;
a first conductive filling layer, filled in a region surrounded by the second electrode layer;
a plurality of sub-auxiliary layers separate from each other, the sub-auxiliary layers covering a top surface of the stack structure, and each of the sub-auxiliary layers being at least overlapped with two capacitor holes;
a second dielectric layer, covering sidewall surfaces and top surfaces of the first electrode layer away from the capacitor holes as well as surfaces of the sub-auxiliary layers; and
a third electrode layer, covering a surface of the second dielectric layer.

8. The structure according to claim 7 , wherein the stack structure comprises a first support layer, a second support layer and a third support layer, and the first support layer, the second support layer and the third support layer are successively stacked along a direction perpendicular to the substrate; and
each of the sub-auxiliary layers covers surfaces of two capacitor holes being overlapped with this sub-auxiliary layer, and covers a surface of the third support layer between two adjacent capacitor holes being overlapped with this sub-auxiliary layer.

9. The structure according to claim 8 , wherein the third support layer has first openings corresponding to gap regions between two adjacent sub-auxiliary layers, and the first openings have a width greater than a width of the gap regions; and
the second support layer has second openings corresponding to the gap regions between two adjacent sub-auxiliary layers.

10. The structure according to claim 8 , wherein the sub-auxiliary layers have a thickness greater than a thickness of the third support layer.

11. The structure according to claim 7 , wherein a material of the sub-auxiliary layers is the same as a material of the support layers.

12. The structure according to claim 7 , further comprising:
a second conductive filling layer, covering a surface of the third electrode layer.

Assignees

• Changxin Memory Tech Inc

Inventors

• Hu Wenjia
• Wu Han
• Lu Yong

Classifications

• H10W44/00

  Electrical arrangements for controlling or matching impedance · CPC title

• H10D1/696 Primary

  comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688) · CPC title

• H10D1/043

  using patterning processes to form electrode extensions, e.g. etching · CPC title

• H10D1/716

  having vertical extensions · CPC title

• H10D1/042 Primary

  using deposition processes to form electrode extensions · CPC title