Semiconductor device and method for operating semiconductor device

Patent metadata

Field	Value
Publication number	US-11916065-B2
Application number	US-202017425348-A
Country	US
Kind code	B2
Filing date	Feb 13, 2020
Priority date	Feb 26, 2019
Publication date	Feb 27, 2024
Grant date	Feb 27, 2024

Abstract

A novel comparison circuit, a novel amplifier circuit, a novel battery control circuit, a novel battery protection circuit, a power storage device, a semiconductor device, an electronic device, and the like are provided. The semiconductor device includes a capacitor, a first amplifier circuit including a first output terminal electrically connected to a first electrode of the capacitor, and a second amplifier circuit including an input terminal, a second output terminal, a first transistor, and a second transistor; a second electrode of the capacitor is electrically connected to the input terminal; the input terminal is electrically connected to a gate of the first transistor and one of a source and a drain of the second transistor; one of a source and a drain of the first transistor is electrically connected to the second output terminal; the second transistor has a function of supplying a potential to the input terminal and holding the potential; and a channel formation region of the second transistor includes a metal oxide containing at least one of indium and gallium.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a first amplifier circuit comprising a first output, terminal;
a capacitor; and
a second amplifier circuit comprising an input terminal, a second output terminal, a first transistor, and a second transistor,
wherein the first output terminal is electrically connected to a first electrode of the capacitor,
wherein a second electrode of the capacitor is electrically connected to a gate of the first transistor and one of a source and a drain of the second transistor through the input terminal,
wherein one of a source and a drain of the first transistor is electrically connected to the second output terminal, and
wherein a channel formation region of the second transistor comprises a metal oxide containing at least one of indium and gallium.

2. A semiconductor device comprising:
a first amplifier circuit comprising a first output, terminal;
a capacitor; and
a second amplifier circuit comprising an input terminal, a second output terminal, a first transistor, a second transistor, and a circuit,
wherein the first output terminal is electrically connected to a first electrode of the capacitor,
wherein a second electrode of the capacitor is electrically connected to a gate of the first transistor and one of a source and a drain of the second transistor through the input terminal,
wherein one of a source and a drain of the first transistor is electrically connected to the second output terminal,
wherein a channel formation region of the second transistor comprises a metal oxide containing at least one of indium and gallium,
wherein the other of the source and the drain of the first transistor is electrically connected to a low potential wiring, and
wherein the circuit is electrically connected to the second output terminal and a high potential wiring.

3. The semiconductor device according to claim 2 ,
wherein the circuit comprises a third transistor,
wherein the second output terminal is electrically connected to one of a source and a drain of the third transistor, and
wherein the high potential wiring is electrically connected to the other of the source and the drain of the third transistor.

4. The semiconductor device according to claim 1 ,
wherein the other of the source and the drain of the first transistor is electrically connected to a low potential wiring.

5. The semiconductor device according to claim 1 ,
wherein the second amplifier circuit further comprises a resistor,
wherein one electrode of the resistor is electrically connected to the second output terminal, and
wherein the other electrode of the resistor is electrically connected to a high potential wiring.

6. The semiconductor device according to claim 2 ,
wherein the circuit comprises a third transistor and a fourth transistor,
wherein one of a source and a drain of the third transistor is electrically connected to the second output terminal,
wherein the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor, and
wherein the other of the source and the drain of the fourth transistor is electrically connected to the high potential wiring.

Assignees

• Semiconductor Energy Lab

Inventors

• Takahashi Kei
• Aoki Takeshi

Classifications

• H02J7/60

  including safety or protection arrangements · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D84/00

  Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers · CPC title

• H10D30/6734

  having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs · CPC title

• H10D87/00

  Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate · CPC title