Semiconductor device and power converter

Patent metadata

Field	Value
Publication number	US-11915988-B2
Application number	US-201917048314-A
Country	US
Kind code	B2
Filing date	Apr 26, 2019
Priority date	Apr 27, 2018
Publication date	Feb 27, 2024
Grant date	Feb 27, 2024

Abstract

A first electrode film is electrically connected to a source region of a semiconductor substrate, and disposed over a main surface of the semiconductor substrate. A second electrode film is electrically connected to a gate electrode, and disposed over the main surface. A third electrode film is disposed over the main surface away from the first electrode film. A protective dielectric film is disposed over the main surface, covers only a portion of each of the first electrode film and the second electrode film and covers at least portion of the third electrode film, and is made of a thermosetting resin. The main surface has a peripheral region and an inner region enclosed by the peripheral region, and the protective dielectric film has a peripheral portion covering the peripheral region and has a first inner portion crossing the inner region and covering at least portion of the third electrode film.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a semiconductor substrate made of a semiconductor having a higher linear expansion coefficient than silicon, the semiconductor substrate including a source region having a first conductivity type, a base region having a second conductivity type different from the first conductivity type, and a drift layer separated from the source region by the base region and having the first conductivity type, the semiconductor substrate having a main surface including a portion formed of the source region;
a gate dielectric film covering the base region of the semiconductor substrate;
a gate electrode facing the base region of the semiconductor substrate through the gate dielectric film;
a first electrode film electrically connected to the source region of the semiconductor substrate, and disposed over the main surface of the semiconductor substrate;
a second electrode film electrically connected to the gate electrode, and disposed over the main surface of the semiconductor substrate away from the first electrode film;
a third electrode film disposed over the main surface of the semiconductor substrate away from the first electrode film; and
a protective dielectric film disposed over the main surface of the semiconductor substrate, the main surface provided with the first electrode film, the second electrode film, and the third electrode film, the protective dielectric film covering only a portion of each of the first electrode film and the second electrode film and covering at least portion of the third electrode film, the protective dielectric film being made of a thermosetting resin, wherein
the main surface of the semiconductor substrate has a peripheral region and an inner region enclosed by the peripheral region, and the protective dielectric film has a peripheral portion covering the peripheral region and has a first inner portion covering at least portion of the third electrode film and crossing the inner region,
the semiconductor device further comprises at least one electrical element connected to the third electrode film, and covered with the first inner portion of the protective dielectric film,
the protective dielectric film has an opening so that the protective film covers less than half of the main surface of the semiconductor substrate,
the opening has an edge in plan view having a first corner portion on a corner side of the main surface, and the first corner portion is curved,
the edge of the opening has, in the plan view, a second corner portion formed with the peripheral region and the first inner portion of the protective dielectric film, and
the first corner portion is curved more gently than the second corner portion,
wherein the at least one electrical element is entirely covered with the first inner portion of the protective dielectric film in plan view and is located in the inner region closer to a center of the semiconductor device than an edge of the semiconductor device.

2. The semiconductor device according to claim 1 , wherein
a portion of the protective dielectric film covering the at least one electrical element has a thickness of 1 μm or more and 20 μm or less.

3. The semiconductor device according to claim 1 , wherein
the third electrode film includes:
a pad portion for electrical connection to an exterior of the semiconductor device; and
a wiring portion having a first end connected to the pad portion and a second end connected to the at least one electrical element.

4. The semiconductor device according to claim 3 , wherein
the second end of the wiring portion is an end of the third electrode film, and is disposed away from the peripheral region of the main surface.

5. The semiconductor device according to claim 3 , wherein
the third electrode film does not cross the inner region of the main surface.

6. The semiconductor device according to claim 3 , wherein
the pad portion is at least partially included in the peripheral region of the main surface.

7. The semiconductor device according to claim 3 , wherein
the at least one electrical element includes a temperature sensor element.

8. The semiconductor device according to claim 1 , wherein
the at least one electrical element includes an electrical element placed in a center of the main surface.

9. The semiconductor device according to claim 1 , wherein
the protective dielectric film has a second inner portion crossing between the peripheral portion and the first inner portion.

10. The semiconductor device according to claim 1 , wherein
the third electrode film is disposed away from the second electrode film.

11. The semiconductor device according to claim 1 , wherein
the at least one electrical element includes at least any one of a diode element, a bipolar transistor element, a resistive element, and a capacitive element.

12. The semiconductor device according to claim 1 , wherein
the gate electrode has a planar structure or a trench structure.

13. The semiconductor device according to claim 1 , wherein
the first inner portion of the protective dielectric film has a tapered cross-sectional shape.

14. The semiconductor device according to claim 1 , wherein
the protective dielectric film is made of at least any one of a polyimide resin, a silicone resin, an epoxy resin, and a polyurethane resin.

15. A power converter comprising:
a main conversion circuit to convert input power for output, the main conversion circuit including the semiconductor device according to claim 1 ;
a drive circuit to output, to the semiconductor device, a drive signal to drive the semiconductor device; and
a control circuit to output, to the drive circuit, a control signal to control the drive circuit.

16. The semiconductor device according to claim 1 , wherein the edge of the opening is an outermost edge.

17. The semiconductor device according to claim 1 ,
wherein the edge of the opening has a third corner portion and a fourth corner portion in the plan view, and the first corner portion is curved more gently than the third corner portion and the fourth corner portion.

18. The semiconductor device according to claim 17 ,
wherein the edge of the opening has a first straight portion between the first corner portion and the second corner portion, a second straight portion between the second corner portion and the third corner portion, a third straight portion between the third corner portion and the fourth corner portion, and a fourth straight portion between the fourth corner portion and the first corner portion.

19. The semiconductor device according to claim 18 ,
wherein, of all the corner portions from the first to the fourth corner portions, the first corner portion is located closest to any corner side of the main surface.

Assignees

• Mitsubishi Electric Corp

Inventors

• Yokogawa Masahiro
• Taguchi Kensuke

Classifications

• H10W74/131

  the semiconductor body being only partially enclosed · CPC title

• H10W40/00

  Arrangements for thermal protection or thermal control (integrated devices comprising arrangements for thermal protection H10D89/60) · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H10W74/47 Primary

  comprising organic materials, e.g. plastics or resins · CPC title

• H10D84/141

  VDMOS having built-in components · CPC title