Transistor manufacturing method

Patent metadata

Field	Value
Publication number	US-11915978-B2
Application number	US-201917291668-A
Country	US
Kind code	B2
Filing date	Nov 15, 2019
Priority date	Nov 29, 2018
Publication date	Feb 27, 2024
Grant date	Feb 27, 2024

Abstract

A first regrowth layer and a second regrowth layer comprising GaAs having high resistance are regrown on a surface of an etching stop layer exposed to the bottom of a first groove and a second groove, and then n-type InGaAs is regrown on the first regrowth layer and the second regrowth layer, whereby a source region and a drain region configured to make contact with a channel layer are formed in the first groove and the second groove respectively.

First claim

The invention claimed is:

1. A manufacturing method for a transistor, comprising:
(i) growing crystals of a barrier layer and a channel layer made of a nitride semiconductor in a c-axis direction on a first substrate;
(ii) preparing a second substrate made of a semiconductor with no nitrogen contained;
(iii) bonding the second substrate to the barrier layer on the first substrate;
(iv) removing the first substrate, wherein the barrier layer and the channel layer remain on the second substrate;
(v) forming, after the first substrate is removed, a first groove and a second groove in the barrier layer and the channel layer, the first groove and the second groove passing through the barrier layer and the channel layer with a region in which a gate electrode is to be formed interposed between the first groove and the second groove;
(vi) forming, in the first groove and the second groove, respectively, a source region and a drain region in contact with the channel layer by regrowing a semiconductor with no nitrogen contained in which impurities are injected from a side of a bottom surface of the first groove and from a side of a bottom surface of the second groove;
(vii) forming a source electrode to be ohmic-connected on the source region and forming a drain electrode to be ohmic-connected on the drain region; and
(viii) forming the gate electrode over the barrier layer and the channel layer between the source electrode and the drain electrode.

2. The manufacturing method for the transistor according to claim 1 , wherein:
a first bonding layer is formed on the barrier layer in step (i);
a second bonding layer is formed on the second substrate in step (ii); and
the first substrate and the second substrate are bonded to each other in a state in which the first bonding layer and the second bonding layer face each other in step (iii).

3. The manufacturing method for the transistor according to claim 1 , wherein the first substrate is removed along with part of the barrier layer in step (iv).

4. The manufacturing method for the transistor according to claim 1 , wherein:
the barrier layer and the channel layer are formed on the first substrate with a sacrificial layer interposed between the first substrate and the barrier layer or the channel layer in step (i); and
the first substrate is removed along with part of the sacrificial layer in step (iv).

5. The manufacturing method for the transistor according to claim 1 , wherein:
in step (i), the channel layer and the barrier layer are grown to be formed in that order on the first substrate by crystal growth in a +c-axis direction, and a gate isolation layer comprising a material having a larger band gap than a band gap of the channel layer is formed in contact with the channel layer between the first substrate and the channel layer; and
in step (viii), the gate electrode is formed on the gate isolation layer.

6. The manufacturing method for the transistor according to claim 1 , wherein:
the barrier layer and the channel layer are grown to be formed in that order on the first substrate by crystal growth in a−c-axis direction in step (i); and
the gate electrode is formed on the barrier layer in step (viii).

7. The manufacturing method for the transistor according to claim 6 , wherein:
the first substrate comprises sapphire, Si, SiC, GaN, or AlN; and
the second substrate comprises GaAs, InP, or Si.

8. The manufacturing method for the transistor according to claim 1 , wherein:
the first substrate comprises sapphire, Si, SiC, GaN, or AlN; and
the second substrate comprises GaAs, InP, or Si.

9. The manufacturing method for the transistor according to claim 1 , wherein:
the channel layer comprises GaN, InGaN, InN or AlGaN, or a layered structure comprising materials selected from the group consisting of GaN, InGaN, InN and AlGaN; and
the barrier layer comprises AlGaN, InAlN, InAIGaN, AlN or GaN, or a layered structure comprising materials selected from the group consisting of AlGaN, InAlN, InAIGaN, AlN and GaN.

10. A manufacturing method for a transistor, comprising:
(i) forming a nucleation layer on a first substrate;
(ii) forming a sacrificial layer on the nucleation layer;
(iii) forming a gate isolation layer on the sacrificial layer;
(iv) forming a channel layer of a first nitride semiconductor on the gate isolation layer, wherein forming the channel layer comprises growing crystals in a c-axis direction;
(v) forming a barrier layer of a second nitride semiconductor on the channel layer, wherein forming the barrier layer comprises growing crystals in the c-axis direction;
(vi) forming a first bonding layer on the barrier layer;
(vii) forming an etching stop layer on a second substrate made of a semiconductor with no nitrogen contained;
(viii) forming a second bonding layer on the etching stop layer;
(ix) bonding the first substrate and the second substrate by bonding the second bonding layer to the first bonding layer;
(x) removing the first substrate;
(xi) exposing a surface of the gate isolation layer by removing the sacrificial layer;
(xii) forming, after the sacrificial layer is removed, a first groove and a second groove through the barrier layer and the channel layer, wherein a region in which a gate electrode is to be formed is interposed between the first groove and the second groove; and
(xiii) forming, in the first groove and the second groove, respectively, a source region and a drain region in contact with the channel layer by regrowing a semiconductor with no nitrogen contained in which impurities are injected from a side of a bottom surface of the first groove and from a side of a bottom surface of the second groove.

11. The manufacturing method for the transistor according to claim 10 , further comprising:
(xiv) forming a source electrode to be ohmic-connected on the source region and forming a drain electrode to be ohmic-connected on the drain region; and
(xv) forming the gate electrode over the barrier layer and the channel layer between the source electrode and the drain electrode.

12. The manufacturing method for the transistor according to claim 10 , wherein forming the nucleation layer, forming the sacrificial layer, forming the gate isolation layer, and forming the first bonding layer each comprise growing crystals in the c-axis direction.

13. The manufacturing method for the transistor according to claim 10 , wherein:
the first substrate comprises sapphire, Si, SiC, GaN, or AlN; and
the second substrate comprises GaAs, InP, or Si.

14. The manufacturing method for the transistor according to claim 13 , wherein:
the channel layer comprises GaN, InGaN, InN or AlGaN, or a layered structure comprising materials selected from the group consisting of GaN, InGaN, InN and AlGaN; and
the barrier layer comprises AlGaN, InAlN, InAIGaN, AlN or GaN, or a layered structure comprising materials selected from the group consisting of AlGaN, InAlN, InAIGaN, AlN and GaN.

15. The manufacturing method for the transistor according to claim 10 , wherein:
the channel layer comprises GaN, InGaN, InN or AlGaN, or a layered structure comprising materials selected from the group consisting of GaN, InGaN, InN and AlGaN; and
the barrier layer comprises AlGaN, InAlN, InAIGaN, AlN or GaN, or a layered structure comprising materials selected from the group consisting of AlGaN, InAlN, InAIGaN, AlN and GaN.

16. The manufacturing method for the transistor according to claim 10 , wherein forming the first bonding layer in step (vi) further comprises:
forming a first main bonding layer on the barrier layer;

Assignees

• Nippon Telegraph & Telephone

Inventors

• Hoshi Takuya
• Yoshiya Yuki
• Sugiyama Hiroki
• Matsuzaki Hideaki

Classifications

• H10P14/3466

  Crystal orientation · CPC title

• H10P14/3416

  Nitrides · CPC title

• H10P14/2921

  being crystalline insulating materials · CPC title

• H10P14/2908

  Nitrides · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title