Pixel circuit and display device including the same

Patent metadata

Field	Value
Publication number	US-11915640-B1
Application number	US-202318119498-A
Country	US
Kind code	B1
Filing date	Mar 9, 2023
Priority date	Aug 2, 2022
Publication date	Feb 27, 2024
Grant date	Feb 27, 2024

Abstract

A pixel circuit includes a light-emitting element, a write transistor writing a data voltage, a driving transistor generating a driving current based on the data voltage and applying the driving current to the light-emitting element, a first initialization transistor applying a first initialization voltage to a control electrode of the driving transistor, a blocking transistor disposed between the light-emitting element and the driving transistor, a first blocking control transistor including a control electrode connected to the control electrode of the driving transistor, a first electrode receiving a first signal, and a second electrode connected to a control electrode of the blocking transistor, and a second blocking control transistor including a control electrode connected to the control electrode of the driving transistor, a first electrode receiving a second signal, and a second electrode connected to the control electrode of the blocking transistor.

First claim

What is claimed is:

1. A pixel circuit comprising:
a light-emitting element;
a write transistor which writes a data voltage;
a driving transistor which generates a driving current based on the data voltage and applies the driving current to the light-emitting element;
a first initialization transistor which applies a first initialization voltage to a control electrode of the driving transistor;
a blocking transistor disposed between the light-emitting element and the driving transistor;
a first blocking control transistor including:
a control electrode connected to the control electrode of the driving transistor;
a first electrode which receives a first signal; and
a second electrode connected to a control electrode of the blocking transistor; and

a second blocking control transistor including a control electrode connected to the control electrode of the driving transistor, a first electrode which receives a second signal, and a second electrode connected to the control electrode of the blocking transistor.

2. The pixel circuit of claim 1 , wherein the first blocking control transistor is a p-type transistor, and
wherein the second blocking control transistor is an n-type transistor.

3. The pixel circuit of claim 2 , wherein the first signal has an inactivation level in an emission period in which the driving current is generated.

4. The pixel circuit of claim 3 , wherein the second signal has an activation level in the emission period.

5. The pixel circuit of claim 1 , wherein the write transistor writes the data voltage in response to a write gate signal, and
wherein the first signal is the write gate signal.

6. The pixel circuit of claim 5 , wherein the blocking transistor is a same type as the write transistor.

7. The pixel circuit of claim 1 , further comprising:
a second initialization transistor which applies a second initialization voltage to an anode electrode of the light-emitting element in response to a bias gate signal,
wherein the first signal is the bias gate signal.

8. The pixel circuit of claim 7 , wherein the blocking transistor is a same type as the second initialization transistor.

9. The pixel circuit of claim 1 , further comprising:
a first emission transistor including a control electrode which receives an emission signal, a first electrode which receives a first power voltage, and a second electrode connected to a first electrode of the driving transistor; and
a second emission transistor including a control electrode which receives the emission signal, a first electrode connected to a second electrode of the driving transistor, and a second electrode connected to a first electrode of the blocking transistor,
wherein the second signal is the emission signal.

10. The pixel circuit of claim 1 , wherein the driving transistor includes the control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node,
wherein the write transistor includes a control electrode which receives a write gate signal, a first electrode which receives the data voltage, and a second electrode connected to the second node,
wherein the first initialization transistor includes a control electrode which receives an initialization gate signal, a first electrode which receives the first initialization voltage, and a second electrode connected to the first node,
wherein the blocking transistor includes the control electrode, a first electrode connected to a fourth node, and a second electrode connected to a fifth node, and
wherein the light-emitting element includes a first electrode connected to the fifth node and a second electrode which receives a second power voltage.

11. The pixel circuit of claim 10 , further comprising:
a compensation transistor including a control electrode which receives a compensation gate signal, a first electrode connected to the third node, and a second electrode connected to the first node;
a first emission transistor including a control electrode which receives an emission signal, a first electrode which receives a first power voltage, and a second electrode connected to the second node;
a second emission transistor including a control electrode which receives the emission signal, a first electrode connected to the third node, and a second electrode connected to the fourth node;
a second initialization transistor including a control electrode which receives a bias gate signal, a first electrode which receives a second initialization voltage, and a second electrode connected to the fifth node; and
a storage capacitor including a first electrode which receives the first power voltage and a second electrode connected to the first node.

12. A display device comprising:
a display panel including pixel circuits;
a data driver which provides a data voltage to each of the pixel circuits;
a gate driver which provides gate signals to each of the pixel circuits; and
a timing controller which controls the data driver and the gate driver,
wherein each of the pixel circuits includes:
a light-emitting element;
a write transistor which writes the data voltage;
a driving transistor which generates a driving current based on the data voltage and applies the driving current to the light-emitting element;
a first initialization transistor which applies a first initialization voltage to a control electrode of the driving transistor;
a blocking transistor disposed between the light-emitting element and the driving transistor;
a first blocking control transistor including:
a control electrode connected to the control electrode of the driving transistor;
a first electrode which receives a first signal; and
a second electrode connected to a control electrode of the blocking transistor; and

a second blocking control transistor including:
a control electrode connected to the control electrode of the driving transistor;
a first electrode which receives a second signal; and
a second electrode connected to the control electrode of the blocking transistor.

13. The display device of claim 12 , wherein the first blocking control transistor is a p-type transistor, and
wherein the second blocking control transistor is an n-type transistor.

14. The display device of claim 13 , wherein the first signal has an inactivation level in an emission period in which the driving current is generated.

15. The display device of claim 14 , wherein the second signal has an activation level in the emission period.

16. The display device of claim 12 , wherein the gate signals includes a write gate signal,
wherein the write transistor writes the data voltage in response to the write gate signal, and
wherein the first signal is the write gate signal.

17. The display device of claim 16 , wherein the blocking transistor is a same type as the write transistor.

18. The display device of claim 12 , wherein the gate signals includes a bias gate signal,
wherein each of the pixel circuits includes a second initialization transistor which applies a second initialization voltage to an anode electrode of the light-emitting element in response to the bias gate signal, and
wherein the first signal is the bias gate signal.

19. The display device of claim 18 , wherein the blocking transistor is a same type as the second initialization transistor.

20. The display device of claim 12 , further comprising:
an emission driver which provides an emission signal to each of the pixel circuits,
wherein the pixel ci

Assignees

• Samsung Display Co Ltd

Inventors

• Shim Donghwan
• Park Kwangwoo
• Lee Eonjoo
• Lee Jin-Yong
• Jang Cheol
• Jo Yongseon

Classifications

• G09G3/32 Primary

  semiconductive, e.g. using light-emitting diodes [LED] · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G2310/0275

  Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current · CPC title

• G09G2310/0278

  Details of driving circuits arranged to drive both scan and data electrodes · CPC title