Reducing memory inconsistencies between synchronized computing devices

Patent metadata

Field	Value
Publication number	US-11915022-B2
Application number	US-201615098910-A
Country	US
Kind code	B2
Filing date	Apr 14, 2016
Priority date	Apr 14, 2016
Publication date	Feb 27, 2024
Grant date	Feb 27, 2024

Abstract

Mechanisms for reducing memory inconsistencies between two synchronized computing devices are provided. A first hypervisor module of a first computing device iteratively determines that content of a memory page of a plurality of memory pages has been modified. The content of the memory page is sent to a second hypervisor module on a second computing device. At least one other memory page of the plurality of memory pages is identified, and a verification value based on the content of the at least one other memory page is generated. The verification value and a memory page identifier that identifies the at least one other memory page is sent to the second hypervisor module on the second computing device.

First claim

What is claimed is:

1. A computing system comprising:
a first computing device comprising:
a first random access memory (RAM) comprising a plurality of memory pages;
a first processor device coupled to the RAM; and
a first hypervisor module that interfaces with the first processor device and is to iteratively:
determine that content of a memory page of the plurality of memory pages has been modified;
send the content of the memory page to a second hypervisor module on a second computing device;

identify, for corruption-detection purposes, at least one other memory page of the plurality of memory pages that was previously sent to the second computing device, the at least one other memory page being identified without receipt of a request from the second computing device related to the at least one other memory page;
generate a verification value based on content of the at least one other memory page; and
send the verification value and a memory page identifier that identifies the at least one other memory page to the second hypervisor module on the second computing device without sending the content of the at least one other memory page to facilitate a determination by the second computing device of whether the at least one other memory page that was previously sent to the second computing device is corrupted.

2. The computing system of claim 1 , wherein to identify the at least one other memory page, the first hypervisor module is further to randomly identify the at least one other memory page from the plurality of memory pages.

3. The computing system of claim 1 , wherein to identify, the at least one other memory page, the first hypervisor module is further to determine that the content of the at least one other memory page is unmodified.

4. The computing system of claim 3 , wherein to determine that the content of the at least one other memory page is unmodified, the first hypervisor module is further to determine that a modified memory page bit associated with the at least one other memory page indicates that the content of the at least one other memory page is unmodified.

5. The computing system of claim 1 , wherein the at least one other memory page comprises a group of memory pages, and the first hypervisor module is further to:
generate a plurality of verification values, each verification value associated with a respective different memory page in the group of memory pages and generated based on content contained in the respective different memory page in the group of memory pages; and
send a group of memory page identifiers, each memory page identifier identifying a corresponding one of the memory pages in the group of memory pages, and the plurality of verification values to the second hypervisor module without sending content of the group of memory pages to allow the second hypervisor module to verify that a copy of the group of memory pages maintained by the second hypervisor module is identical to the group of memory pages.

6. The computing system of claim 1 , wherein:
the at least one other memory page comprises a group of memory pages;
to generate the verification value based on the content of the at least one other memory page, the first hypervisor module is further to generate the verification value based on content of each memory page in the group of memory pages; and
to send the verification value and the memory page identifier that identifies the at least one other memory page to the second hypervisor module on the second computing device, the first hypervisor module is further to send a group of memory page identifiers, each memory page identifier identifying a corresponding one of the memory pages in the group of memory pages, and the verification value to the second hypervisor module without sending content of the group of memory pages to allow the second hypervisor module to verify that a copy of the group of memory pages maintained by the second hypervisor module is identical to the group of memory pages.

7. The computing system of claim 1 , wherein the first hypervisor module is further to mark the content of the memory page as being unmodified.

8. The computing system of claim 1 , wherein the verification value is a MD 5 hash value.

9. The computing system of claim 1 , wherein to identify the at least one other memory page, the first hypervisor module is to further:
identify the at least one other memory page from a set of memory pages identified on a page list of memory pages; and
remove the at least one other memory page from the page list.

10. The computing system of claim 1 , wherein the memory page identifier is a memory page address.

11. The computing system of claim 1 , wherein the first hypervisor module is to further:
receive a request from the second computing device for the content of the at least one other memory page; and
send the content of the at least one other memory page to the second computing device in response to the request from the second computing device for the content of the at least one other memory page.

12. The computing system of claim 1 further comprising:
the second computing device comprising:
a second RAM;
a second processor device coupled to the second RAM; and

the second hypervisor module that interfaces with the second processor device and is to:
receive the at least one other memory page of the plurality of memory pages;
copy the at least one memory page into a memory page of the second RAM;
subsequent to receiving the at least one other memory page, receive the verification value and the memory page identifier;
in response to receiving the verification value and the memory page identifier, access the at least one other memory page identified by the memory page identifier and determine that the memory page of the second RAM has not become corrupted based on the verification value; and
in response to determining that the memory page of the second RAM has not become corrupted, not sending a request to the first computing device for a copy of the at least one other memory page.

13. A method comprising:
determining, by a first hypervisor module executing on a first computing device comprising a first processor device, that content of a memory page of a plurality of memory pages in a random access memory (RAM) has been modified;
sending the content of the memory page to a second hypervisor module on a second computing device;
identifying, for corruption-detection purposes, at least one other memory page of the plurality of memory pages that was previously sent to the second computing device the at least one other memory page being identified without receipt of a request from the second computing device;
generating a first verification value based on content of the at least one other memory page;
sending, without receipt of a request from the second hypervisor module for the first verification value, the first verification value and a memory page identifier that identifies the at least one other memory page to the second hypervisor module on the second computing device without sending the content of the at least one other memory page;
receiving, by the second hypervisor module, the at least one other memory page of the plurality of memory pages;
copying the at least one other memory page into a memory page of a second RAM;
subsequent to receiving the at least one other memory page, receiving the first verification value and the memory page identifier;
in response to receiving the first verification value and the memory page identifier, accessing the at least one other memory page identified by the memory page identifier and determining that the mem

Assignees

• Red Hat Inc

Inventors

• Gilbert David A

Classifications

• G06F9/45558 Primary

  Hypervisor-specific management and integration aspects · CPC title

• G06F11/165

  with continued operation after detection of the error · CPC title

• G06F11/1637

  using additional compare functionality in one or some but not all of the redundant processing components · CPC title

• G06F11/1666

  where the redundant component is memory or memory area · CPC title

• G06F11/1675

  Temporal synchronisation or re-synchronisation of redundant processing components · CPC title