Cache memory device and data cache method

Patent metadata

Field	Value
Publication number	US-11914515-B2
Application number	US-202218048161-A
Country	US
Kind code	B2
Filing date	Oct 20, 2022
Priority date	Dec 1, 2021
Publication date	Feb 27, 2024
Grant date	Feb 27, 2024

Abstract

A cache memory device is provided in the disclosure. The cache memory device includes a first AGC, a compression circuit, a second AGC, a virtual tag array, and a comparator circuit. The first AGC generates a virtual address based on a load instruction. The compression circuit obtains the higher part of the virtual address and generates a target hash value based on the higher part of the virtual address. The second AGC generates the lower part of the virtual address based on the load instruction. The virtual tag array obtains the lower part and selects a set of memory units. The comparator circuit compares the target hash value to a hash value stored in each memory unit of the set of memory units. When the comparator circuit generates the virtual tag miss signal, the comparator circuit transmits the virtual tag miss signal to the reservation station.

First claim

What is claimed is:

1. A cache memory device, comprising:
a reservation station, outputting a load instruction; and
a memory order buffer (MOB) circuit, coupled to the reservation station,
wherein the MOB circuit comprises:
a first address generation circuit (AGC), generating a virtual address based on the load instruction from the reservation station;
a compression circuit, coupled to the first AGC, obtaining a higher part of the virtual address from the first AGC and generating a target hash value based on the higher part of the virtual address;
a second AGC, generating a lower part of the virtual address based on the load instruction;
a virtual tag array, coupled to the second AGC, obtaining the lower part of the virtual address from the second AGC and selecting a set of memory units from the virtual tag array; and
a comparator circuit, coupled to the compression circuit and the virtual tag array, comparing the target hash value to a hash value stored by each memory unit of the set of memory units to generate a virtual tag hit signal or a virtual tag miss signal, wherein when the comparator circuit generates the virtual tag miss signal; the MOB circuit transmits the virtual tag miss signal to the reservation station.

2. The cache memory device of claim 1 , wherein the virtual tag array comprises a plurality of sets of memory units, wherein the hash value stored by each memory unit of the plurality of sets of memory units is generated based on the higher part of the virtual address corresponding to each memory unit; and the MOB circuit transmits the virtual tag miss signal to the reservation station to indicate the reservation station to reserve information related to the load instruction.

3. The cache memory device of claim 1 , wherein the MOB circuit further comprises a correction circuit, wherein the correction circuit is coupled to the comparator circuit, and wherein when the comparator circuit generates the virtual tag hit signal, the comparator circuit transmits the virtual tag hit signal to the correction circuit.

4. The cache memory device of claim 3 , wherein when the correction circuit receives the virtual tag hit signal and a physical tag hit signal, the correction circuit determines whether first hit information corresponding to the virtual tag hit signal matches second hit information corresponding to the physical tag hit signal.

5. The cache memory device of claim 4 , further comprising:
a reorder buffer (ROB),
wherein when the first hit information does not match the second hit information, the correction circuit updates the virtual tag array based on the second hit information and transmits the virtual tag hit signal, the physical tag hit signal and synchronization information to the ROB, and the ROB transmits a replay signal to the reservation station.

6. The cache memory device of claim 3 , further comprising:
a reorder buffer (ROB),
wherein when the correction circuit receives the virtual tag hit signal and a physical tag miss signal, the correction circuit transmits the virtual tag hit signal and the physical tag miss signal to the ROB, and the ROB transmits a replay signal to the reservation station.

7. The cache memory device of claim 3 , wherein the comparator circuit further comprising a first comparator circuit, a second comparator circuit and a third comparator circuit; wherein
the first comparator circuit compares the target hash value generated by the compression circuit to the hash value in virtual tag array to determine whether the target hash value hits one way of a set of memory units;
the second comparator circuit obtains the higher part VA[H] of the virtual address generated by the first AGC and determines whether the higher part VA[H] hits one way of the set of memory units;
when the higher part VA[H] of the virtual address hits one way of the set of memory units, the second comparator circuit obtains the physical address PA corresponding to the higher part VA[H], and transmit the physical address PA to the third comparator circuit; and
the third comparator circuit determines whether the higher part PA[H] of the physical address PA hits one way of the set of memory units.

8. The cache memory device of claim 7 , wherein when the target hash value does not hit one way of the set of memory units, the first comparator circuit generates a virtual tag miss signal.

9. The cache memory device of claim 7 , wherein when the higher part PA[H] hits one way of the set of memory units, the third comparator circuit asserts the physical tag hit signal, and when the higher part PA[H] does not hit any one way of the set of memory units, the third comparator circuit asserts the physical tag miss signal; the third comparator circuit transmits the physical tag hit signal or the physical tag miss signal to the correction circuit.

10. A data cache method, applied in a cache memory device, comprising:
outputting, by a reservation station of the cache memory device, a load instruction to a memory order buffer (MOB) circuit of the cache memory device;
generating, by a first address generation circuit (AGC) of the MOB circuit, a virtual address based on the load instruction from the reservation station;
obtaining, by a compression circuit of the MOB circuit, a higher part of the virtual address from the first AGC and generating, by the compression circuit, a target hash value based on the higher part of the virtual address;
generating, by a second AGC of the MOB circuit, a lower part of the virtual address based on the load instruction;
obtaining, by a virtual tag array of the MOB circuit, the lower part of the virtual address from the second AGC and selecting, by the virtual tag array, a set of memory units from the virtual tag array;
comparing, by a comparator circuit of the MOB circuit, the target hash value to a hash value stored by each memory unit of the set of memory units to generate a virtual tag hit signal or a virtual tag miss signal; and
when the comparator circuit generates the virtual tag miss signal, transmitting, by the MOB circuit, the virtual tag miss signal to the reservation station.

11. The data cache method of claim 10 , wherein the virtual tag array comprises a plurality of sets of memory units, wherein the hash value stored by each memory unit of the plurality of sets of memory units is generated based on the higher part of the virtual address corresponding to each memory unit and the MOB circuit transmits the virtual tag miss signal to the reservation station to indicate the reservation station to reserve information related to the load instruction.

12. The data cache method of claim 10 , further comprising:
when the comparator circuit generates the virtual tag hit signal, transmitting, by the comparator circuit, the virtual tag hit signal to a correction circuit of the MOB circuit.

13. The data cache method of claim 12 , further comprising:
when the correction circuit receives the virtual tag hit signal and a physical tag hit signal, determining, by the correction circuit whether a first hit information corresponding to the virtual tag hit signal matches a second hit information corresponding to the physical tag hit signal.

14. The data cache method of claim 13 , further comprising:
when the first hit information does not match the second hit information, updating, by the correction circuit, the virtual tag array based on the second hit information;
transmitting, by the correction circuit, the virtual tag hit signal, the physical tag hit signal and synchronization information to a reorder buffer (ROB) of the cache memory device; and
transmitting, by the ROB, a replay sig

Assignees

• Shanghai Zhaoxin Semiconductor Co Ltd

Inventors

• Zhang Junjie
• Yang Mengchen
• Qiao Jing
• Wang Jianbin

Classifications

• G06F9/38

  Concurrent instruction execution, e.g. pipeline or look ahead · CPC title

• G06F12/0846 Primary

  Cache with multiple tag or data arrays being simultaneously accessible · CPC title

• G06F12/0875

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F12/0802 Primary

  Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches · CPC title

• G06F12/0864 Primary

  using pseudo-associative means, e.g. set-associative or hashing · CPC title