Display panel and manufacturing method thereof, and display device

Patent metadata

Field	Value
Publication number	US-11910668-B2
Application number	US-202017419325-A
Country	US
Kind code	B2
Filing date	Feb 27, 2020
Priority date	Feb 27, 2020
Publication date	Feb 20, 2024
Grant date	Feb 20, 2024

Abstract

Provided are a display panel and a manufacturing method thereof, and a display device. At least one sub-pixel comprises a light emitting element; a first transistor comprising a first active layer comprising first and second electrode regions connected to data line and power line respectively; a capacitor; a second transistor comprising a second active layer; a third transistor comprising a third gate connected to a reset line, and a third active layer comprising a third channel region. Orthographic projections of the power line, the reset line, the third channel region and the data line are first, second, third and fourth projections respectively. The region of first, second, and third projections overlapping with each other is first region, and regions of first projection overlapping with second projection and not overlapping with third projection comprise a third region and a second region having an area not smaller than the third region.

First claim

What is claimed is:

1. A display panel, comprising a substrate and a plurality of sub-pixels located on the substrate, at least one sub-pixel of the plurality of sub-pixels comprising:
a light emitting element comprising an anode and a cathode;
a first transistor comprising a first active layer and a first gate which is connected to a scan line, the first active layer comprising a first electrode region, a second electrode region, and a first channel region located between the first electrode region and the second electrode region, wherein the first electrode region is connected to a data line, and the second electrode region is connected to a power line;
a capacitor comprising a first electrode plate and a second electrode plate connected to the power line;
a second transistor comprising a second active layer and a second gate which is connected to the first electrode plate, the second active layer comprising a third electrode region, a fourth electrode region, and a second channel region located between the third electrode region and the fourth electrode region, wherein the third electrode region is connected to the second electrode region, and the fourth electrode region is connected to the anode; and
a third transistor comprising a third active layer and a third gate which is connected to a reset line, the third active layer comprising a fifth electrode region, a sixth electrode region, and a third channel region located between the fifth electrode region and the sixth electrode region, wherein the fifth electrode region is connected to the first electrode plate, and the sixth electrode region is connected to an initialization voltage line,
wherein an orthographic projection of the power line on the substrate is a first projection, an orthographic projection of the reset line on the substrate is a second projection, an orthographic projection of the third channel region on the substrate is a third projection, and an orthographic projection of the data line on the substrate is a fourth projection, and
wherein an region of the first projection overlapping with the second projection and the third projection is a first region, and regions of the first projection overlapping with the second projection and not overlapping with the third projection comprise a second region and a third region that are adjacent to the first region, wherein the second region is located on one side of the first region proximate to the fourth projection, and the third region is located on one side of the first region away from the fourth projection, and an area of the second region is not smaller than an area of the third region.

2. The display panel according to claim 1 , wherein the third projection comprises a first portion and a second portion spaced apart from each other, wherein the first portion is located within the first projection, and the second portion is located outside the first projection.

3. The display panel according to claim 1 , wherein the area of the second region is greater than the area of the third region.

4. The display panel according to claim 1 , wherein each of the first region, the second region, and the third region is in a shape of rectangle.

5. The display panel according to claim 1 , further comprising a shielding layer, wherein:
an orthographic projection of the first electrode region of the first active layer on the substrate is a fifth projection;
an orthographic projection of the fifth electrode region of the third active layer on the substrate is a sixth projection; and
an orthographic projection of the shielding layer on the substrate is a seventh projection, wherein the seventh projection is at least partially located between the fifth projection and the sixth projection.

6. The display panel according to claim 5 , wherein at least one of the fifth projection or the sixth projection at least partially overlaps with the seventh projection.

7. The display panel according to claim 6 , wherein at least one of the fifth projection or the sixth projection is located within the seventh projection.

8. The display panel according to claim 5 , wherein the first active layer and the third active layer are located in a same layer, and the shielding layer is located between the same layer and the substrate.

9. The display panel according to claim 5 , wherein the shielding layer comprises a metal layer.

10. The display panel according to claim 9 , wherein the metal layer comprises a first metal layer, a second metal layer, and a third metal located between the first metal layer and the second metal layer.

11. The display panel according to claim 10 , wherein a material of the first metal layer is the same as a material of the second metal layer, and different from a material of the third metal layer.

12. The display panel according to claim 11 , wherein the material of the first metal layer and the material of the second metal layer comprise Ti, and the material of the third metal layer comprises Al.

13. The display panel according to claim 1 , wherein the at least one sub-pixel further comprises at least one of:
a fourth transistor comprising a fourth active layer and a fourth gate which is connected to the scan line, the fourth active layer comprising a seventh electrode region, an eighth electrode region, and a fourth channel region located between the seventh electrode region and the eighth electrode region, wherein the seventh electrode region is connected to the second gate, and the eighth electrode region is connected to the fourth electrode region;
a fifth transistor comprising a fifth active layer and a fifth gate which is connected to a control line, the fifth active layer comprising a ninth electrode region, a tenth electrode region, and a fifth channel region located between the ninth electrode region and the tenth electrode region, wherein the ninth electrode region is connected to the power line, and the tenth electrode region is connected to the second electrode region;
a sixth transistor comprising a sixth active layer and a sixth gate connected to the control line, the sixth active layer comprising an eleventh electrode region, a twelfth electrode region, and a sixth channel region located between the eleventh electrode region and the twelfth electrode region, wherein the eleventh electrode region is connected to the fourth electrode region, and the twelfth electrode region is connected to the anode; or
a seventh transistor comprising a seventh active layer and a seventh gate which is connected to the reset line, the seventh active layer comprising a thirteenth electrode region, a fourteenth electrode region, and a seventh channel region located between the thirteenth electrode region and the fourteenth electrode region, wherein the thirteenth electrode region is connected to the twelfth electrode region, and the fourteenth electrode region is connected to the initialization voltage line.

14. The display panel according to claim 13 , wherein the first active layer, the second active layer, the third active layer, the fourth active layer, the fifth active layer, the sixth active layer and the seventh active layer are located in a same layer.

15. The display panel according to claim 1 , wherein the second electrode plate and the initialization voltage line are located in a same layer.

16. The display panel according to claim 1 , wherein the scan line, the first electrode plate and the reset line are located in a same layer.

17. The display panel according to claim 1 , wherein the data line and the power line are located in a same layer.

18

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Guo Yonglin
• Zhang Kai
• Cao Dan
• Lee Sangwon

Classifications

• H10K71/00

  Manufacture or treatment specially adapted for the organic devices covered by this subclass · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10K59/1213 Primary

  the pixel elements being TFTs · CPC title

• H10K59/126

  Shielding, e.g. light-blocking means over the TFTs · CPC title

• H10K59/1216

  the pixel elements being capacitors · CPC title