Display device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-11910658-B2
Application number	US-201916771699-A
Country	US
Kind code	B2
Filing date	Oct 29, 2019
Priority date	Aug 20, 2019
Publication date	Feb 20, 2024
Grant date	Feb 20, 2024

Abstract

The present disclosure provides a display device and a manufacturing method thereof. The display device includes a display region and a non-display region surrounding the display region. The display region includes a main display region and an auxiliary region surrounding the main display region. The auxiliary region is between the non-display region and the main display region. The non-display region includes a bending region connected to the auxiliary region. The display device includes an array substrate including a plurality of pixels units, first trough holes, and second trough holes in the display region. The first trough holes and the second trough holes are disposed in the auxiliary region. The second trough holes are disposed between two adjacent pixel units. An anode electrode is disposed on the array substrate. The first trough holes are disposed in each the pixel units and directly below the anode electrode.

First claim

What is claimed is:

1. A display device, comprising:
a display region;
a non-display region surrounding the display region, wherein the display region comprises a main display region and an auxiliary region surrounding the main display region, the auxiliary region is disposed between the non-display region and the main display region, and the non-display region comprises a bending region connected to the auxiliary region;
an array substrate disposed in the display region and comprising a plurality of pixel units, a plurality of first trough holes, and a plurality of second trough holes, wherein the first trough holes and the second trough holes are disposed in the auxiliary region between the bending region and the main display region, and the second trough holes are disposed between two adjacent pixel units; and
an anode electrode disposed on the array substrate, wherein the first trough holes are correspondingly disposed in each of the pixel units and are disposed directly below the anode electrode,
wherein the array substrate comprises:
a base substrate extending from the display region to the non-display region;
a blocking layer disposed on the base substrate and extending from the display region to the non-display region;
a buffer layer disposed on the blocking layer and extending from the display region to the non-display region;
an active layer disposed on the buffer layer in the display region;
a first gate insulating layer covering the active layer and the buffer layer and extending from the display region to the non-display region;
a first gate layer covering the first gate insulating layer in the display region; a second gate insulating layer covering the first gate layer and the first gate insulating layer, and extending from the display region to the non-display region;
a second gate layer covering the second gate insulating layer in the display region;
a dielectric interlayer covering the second gate insulating layer and the second gate layer, and extending from the display region to the non-display region;
a source electrode and a drain electrode disposed on the dielectric interlayer in the display region and correspondingly connected to the active layer; and
a planarization layer covering the source electrode, the drain electrode, and the dielectric interlayer and extending from the display region to the non-display region, wherein the anode electrode is correspondingly disposed on the planarization layer and is correspondingly connected to the drain electrode;
wherein the first trough holes extend from the dielectric interlayer to a surface of the active layer, and the second trough holes extend from the dielectric interlayer to the blocking layer or to an inside of the buffer layer,
wherein the second trough holes are further disposed between one of the pixel units close to the main display region and the main display region, and disposed between one of the pixel units close to the bending region and the bending region, and
the first trough holes and the second trough holes are filled with an inorganic material adopted by the planarization layer.

2. The display device according to claim 1 , wherein the array substrate further comprises:
a pixel defining layer covering the planarization layer and extending from the display region to the non-display region.

3. The display device according to claim 2 , wherein in the auxillary region, each of the pixel units corresponds to the source electrode, the drain electrode, and at least one of the first trough holes, and the at least one of the first trough holes is disposed between the source electrode and the drain electrode of one of the corresponding pixel units.

4. The display device according to claim 2 , wherein the array substrate further comprises:
a third trough hole disposed in the bending region and extending from the dielectric interlayer to the blocking layer or to the inside of the buffer layer; and
a filling layer filled in the third trough hole.

5. A manufacturing method for manufacturing the display device according to claim 1 , comprising:
forming the array substrate, forming the pixel units, wherein the auxiliary region is between the bending region and the main display region, the first trough holes are formed in each of the pixel units, and the second trough holes are formed between two adjacent pixel units, wherein the second trough holes are further disposed between one of the pixel units close to the main display region and the main display region, and disposed between one of the pixel units close to the bending region and the bending region; and
forming the anode electrode on the array substrate, and the first trough holes are disposed directly below the anode electrode,
wherein forming the array substrate comprises:
forming a base substrate extending from the display region to the non-display region;
forming a blocking layer on the base substrate in the display region and the non-display region;
forming a buffer layer on the blocking layer in the display region and the non-display region;
forming an active layer on the buffer layer in the display region;
forming a first gate insulating layer on the active layer and the buffer layer in the display region and the non-display region;
forming a first gate layer on the first gate insulating layer in the display region;
forming a second gate insulating layer on the first gate insulating layer and the first gate layer in the display region and the non-display region;
forming a second gate layer on the second gate insulating layer in the display region; and
forming a dielectric interleaver on the second gate insulating layer and the second gate layer in the display region;
wherein in each of the pixel units in the display region, two via holes are formed and extended from the dielectric interlayer to a surface of the active layer, and the first trough holes are simultaneously formed between the two via holes in the auxiliary region;
between two adjacent pixel units in the auxiliary region, the second trough holes are formed and extended from the dielectric interlayer to the blocking layer or extended from the dielectric interlayer to an inside of the buffer layer;
depositing a metal material in the via holes and forming a source electrode and a drain electrode in the dielectric interlayer; and
depositing an inorganic material in the first trough holes and the second trough holes and forming a planarization layer on surfaces of the dielectric interlayer, the source electrode, and the drain electrode.

6. The manufacturing method according to claim 5 , wherein forming the anode electrode on the array substrate comprises: forming the anode electrode on the planarization layer in the display region, wherein the anode electrode is disposed directly above the first trough holes in the auxiliary region, and forming a pixel defining layer on the planarization layer in the display region and the non-display region after forming the anode electrode on the array substrate.

7. The manufacturing method according to claim 5 , wherein while forming the second trough holes extending from the dielectric interlayer to the blocking layer or extending from the dielectric interlayer to the inside of the buffer layer, forming a third trough hole extending from the dielectric interlayer to the blocking layer or extending from the dielectric interlayer to the inside of the buffer layer in the bending region of the non-display region;
filling the third trough hole with an organic photoresist material to form a filling layer before forming the source electrode and the drain electrode; and
forming metal wires on the filling layer while forming the source electrode and the drain electrode.

Assignees

• Wuhan China Star Optoelectronics Semiconductor Display Tech Co Ltd

Inventors

• Ouyang Qi
• Zheng Min

Classifications

• H10K59/123 Primary

  Connection of the pixel electrodes to the thin film transistors [TFT] · CPC title

• H10K59/1201

  Manufacture or treatment · CPC title

• H10K59/122

  Pixel-defining structures or layers, e.g. banks · CPC title

• H10K59/124 Primary

  Insulating layers formed between TFT elements and OLED elements · CPC title

• H10K59/1213

  the pixel elements being TFTs · CPC title