Three dimensional semiconductor device and method of forming the same

Patent metadata

Field	Value
Publication number	US-11910614-B2
Application number	US-202217711826-A
Country	US
Kind code	B2
Filing date	Apr 1, 2022
Priority date	Mar 9, 2017
Publication date	Feb 20, 2024
Grant date	Feb 20, 2024

Abstract

A three-dimensional semiconductor device and a method of forming the same are provided. The three-dimensional semiconductor device comprises a substrate including first and second areas; first and second main separation patterns, disposed on the substrate and intersecting the first and second areas; gate electrodes disposed between the first and second main separation patterns and forming a stacked gate group, the gate electrodes sequentially stacked on the first area and extending in a direction from the first area to the second area; and at least one secondary separation pattern disposed on the second area, disposed between the first and second main separation patterns, and penetrating through the gate electrodes disposed on the second area. The gate electrodes include pad portions on the second area, and the pad portions are thicker than the gate electrodes disposed on the first area and in contact with the at least one secondary separation pattern.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first main separation structure and a second main separation structure disposed on a substrate and extending from a first area to a second area;
a plurality of word lines stacked in the first area in a vertical direction perpendicular to an upper surface of the substrate and extended to the second area, the plurality of word lines disposed between the first main separation structure and the second main separation structure;
a plurality of secondary separation structures disposed in the second area, between the first main separation structure and the second main separation structure, and penetrating through the plurality of word lines; and
channel structures disposed in the first area, between the first main separation structure and the second main separation structure, and penetrating through the plurality of word lines;
wherein each of the plurality of word lines in the second area includes extension portions spaced apart from each other by the plurality of secondary separation structures,
wherein each of the extension portions extends in a first direction parallel to the upper surface of the substrate,
wherein the extension portions include a first extension portion and a second extension portion spaced apart from each other by a first secondary separation structure of the plurality of secondary separation structures,
wherein the plurality of word lines include a first word line and a second word line on the first word line,
wherein the first word line further includes a first pad region extending from the first extension portion of the first word line in the first direction,
wherein the second word line further includes a second pad region extending from the second extension portion of the second word line and a protruding portion extending from the first extension portion of the second word line,
wherein a width in a second direction of the second pad region of the second word line is different from a width in the second direction of the protruding portion of the second word line,
wherein the second direction is perpendicular to the first direction, and
wherein the protruding portion of the second word line vertically overlaps a portion of the first pad region of the first word line.

2. The semiconductor device of claim 1 , wherein the width in the second direction of the second pad region of the second word line is greater than the width in the second direction of the protruding portion of the second word line.

3. The semiconductor device of claim 1 , further comprising gate contact plugs,
wherein the first pad region includes a first pad portion and a first dummy portion,
wherein the second pad region includes a second pad portion and a second dummy portion, and
wherein the gate contact plugs include:
a first gate contact plug contacting the first pad portion and spaced apart from the first dummy portion, and
a second gate contact plug contacting the second pad portion and spaced apart from the second dummy portion.

4. The semiconductor device of claim 3 , wherein a thickness of each of the first and second pad portions is greater than a thickness of each of the first and second dummy portions.

5. The semiconductor device of claim 3 , wherein a width in the second direction of each of the first and second pad portions is different from a width in the second direction of each of the first and second dummy portions.

6. The semiconductor device of claim 5 , wherein the width in the second direction of each of the first and second pad portions is greater than the width in the second direction of each of the first and second dummy portions.

7. The semiconductor device of claim 3 , wherein the protruding portion of the second word line vertically overlaps the first dummy portion of the first pad region.

8. The semiconductor device of claim 7 , wherein the protruding portion of the second word line does not vertically overlap the first pad portion of the first pad region.

9. The semiconductor device of claim 3 , wherein a thickness of each of the protruding portion, the first pad portion, and the second pad portion is greater than a thickness of each of the first and second dummy portions.

10. The semiconductor device of claim 1 , wherein a thickness of the protruding portion is greater than a thickness of the first extension portion.

11. A semiconductor device, comprising:
a first main separation structure and a second main separation structure disposed on a substrate and extending from a first area to a second area;
a plurality of word lines stacked in the first area in a vertical direction perpendicular to an upper surface of the substrate and extended to the second area, the plurality of word lines being between the first main separation structure and the second main separation structure;
a plurality of secondary separation structures disposed in the second area, between the first main separation structure and the second main separation structure, and penetrating through the plurality of word lines;
channel structures disposed in the first area, between the first main separation structure and the second main separation structure, and penetrating through the plurality of word lines; and
gate contact plugs,
wherein each of the plurality of word lines in the second area include extension portions spaced apart from each other by the plurality of secondary separation structures, and a pad region extending from one of the extension portions,
wherein the plurality of word lines include a first word line, a second word line on the first word line, a third word line on the second word line, and a fourth word line on the third word line,
wherein at least two of the second, third, and fourth word lines in the second area further include a respective protruding portion extending from one of the extension portions, and spaced apart from the pad regions and the gate contact plugs.

12. The semiconductor device of claim 11 , wherein the protruding portions do not vertically overlap each other, and
wherein the pad regions do not vertically overlap each other.

13. The semiconductor device of claim 12 , wherein a first protruding portion of the protruding portions vertically overlaps a portion of a first pad region of the pad regions, and
wherein the first protruding portion is at a higher level than the first pad region.

14. The semiconductor device of claim 11 , wherein a plurality of secondary separation structures include:
a first secondary separation structure disposed in the second area, between the first main separation structure and the second main separation structure, and penetrating through the plurality of word lines;
a second secondary separation structure disposed in the second area, between the first main separation structure and the first secondary separation structure, and penetrating through the plurality of word lines; and
a third secondary separation structure disposed in the second area, between the second main separation structure and the first secondary separation structure, and penetrating through the plurality of word lines,
wherein the extension portions of each of the plurality of word lines include a first extension portion, a second extension portion, a third extension portion and a fourth extension portion,
wherein the first extension portion is between the first main separation structure and the second secondary separation structure,
wherein the second extension portion is between the first secondary separation structure and the second secondary separation structure,
wherein the third extension portion is between the fi

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Chang Sup
• Nam Phil Ouk
• Lee Sung Yun
• Kang Chang Seok

Classifications

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10D84/0142

  the gate conductors having different shapes or dimensions · CPC title

• H10B43/50 Primary

  characterised by the boundary region between the core and peripheral circuit regions · CPC title