Anti-fraud control system, monitoring device, and anti-fraud control method

US11909748B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11909748-B2
Application numberUS-202117224883-A
CountryUS
Kind codeB2
Filing dateApr 7, 2021
Priority dateNov 2, 2018
Publication dateFeb 20, 2024
Grant dateFeb 20, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

In an anti-fraud control system, a first error monitoring device includes a first frame transmitting and receiving unit that receives a frame flowing on the on-board network; and a first error detector that causes transmission of an error notification frame for notifying of an occurrence of an error in the frame when detecting the occurrence of the error in the frame received by the first frame transmitting and receiving unit. Each of second error monitoring devices includes: a second frame transmitting and receiving unit that receives the error notification frame; and a second error detector that regards, as a frame to be invalidated, the frame subjected to the error and included in the received error notification frame, and shifts the second error monitoring device to an invalidation mode for invalidating reception of subsequent frames, if no error is detected in an own branch with respect to the frame.

First claim

Opening claim text (preview).

What is claimed is: 1. An anti-fraud control system in an onboard network under a time-triggered communication protocol based on time slots, the on-hoard network being connected, for each of branches, to one or more electronic control devices each transmitting and receiving a frame within a predetermined time slot, the anti-fraud control system comprising: error monitoring devices each for a corresponding one of the branches, wherein a first error monitoring device among the error monitoring devices includes: a first frame transmitting and receiving hardware unit that receives the frame flowing on the on-board network; and a first hardware error detector that monitors whether an error occurs in the frame received by the first frame transmitting and receiving hardware unit, and causes the first frame transmitting and receiving hardware unit to transmit an error notification frame when detecting an occurrence of an error in the frame received by the first frame transmitting and receiving hardware unit, the error notification frame containing information identifying a type of the frame subjected to the error and for notifying of the occurrence of the error in the frame, and each of one or more second error monitoring devices different from the first error monitoring device among the error monitoring devices includes: a second frame transmitting and receiving hardware unit that receives the error notification frame; and a second hardware error detector that regards, as a frame to be invalidated, the frame subjected to the error and included in the error notification frame received, and shifts the second error monitoring device to an invalidation mode for invalidating reception of subsequent frames, when no error is detected in the corresponding one of the branches with respect to the frame. 2. The anti-fraud control system according to claim 1 , wherein in each of the one or more second error monitoring devices, the second frame transmitting and receiving hardware unit transmits/receives a frame within a predetermined time slot of the on-board network, and when the second error monitoring device is in the invalidation mode, the second hardware error detector invalidates reception of the frame to be invalidated by causing the second frame transmitting and receiving hardware unit not to receive the frame to be invalidated or by causing the second frame transmitting and receiving hardware unit to transmit a frame having a same identifier as the frame to be invalidated in a same time slot as the frame to be invalidated. 3. The anti-fraud control system according to claim 2 , wherein in the first error monitoring device, when detecting that no error notification frame for notifying of an occurrence of an error in the corresponding one of the branches is received from the one or more second error monitoring devices with respect to the frame subjected to the error and included in the error notification frame transmitted by the first frame transmitting and receiving hardware unit, the first hardware error detector causes the first frame transmitting and receiving hardware unit to transmit an mode transition frame for shifting the one or more second error monitoring devices to the invalidation mode, and in each of the one or more second error monitoring devices, when detecting that the second frame transmitting and receiving hardware unit has received the mode transition frame, the second hardware error detector determines that no error is detected in the corresponding one of the branches and shifts the second error monitoring device to the invalidation mode. 4. The anti-fraud control system according to claim 2 , wherein in the first error monitoring device, when detecting that no error notification frame for notifying of an occurrence of an error in the corresponding one of the branches is received from the one or more second error monitoring devices with respect to the frame subjected to the error and included in the error notification frame transmitted by the first frame transmitting and receiving hardware unit, the first hardware error detector causes the first frame transmitting and receiving hardware unit to transmit the mode transition frame for shifting the one or more second error monitoring devices to the invalidation mode, the first hardware error detector further monitors whether an error occurs in the mode transition frame transmitted by the first frame transmitting and receiving hardware unit, and causes the first frame transmitting and receiving hardware unit to transmit an anomaly notification frame for notifying of an occurrence of an anomaly in transmitting and receiving the mode transition frame, when detecting the occurrence of the error in the mode transition frame, and in each of the one or more second error monitoring devices, when detecting that the second frame transmitting and receiving hardware unit has received the anomaly notification frame, the second hardware error detector shifts the second error monitoring device to the invalidation mode. 5. The anti-fraud control system according to claim 2 , wherein each of the one or more second error monitoring devices further includes an error state holder that holds at least one of a total number of error detections or a total number of receptions of an error notification frame for each frame type, in the first error monitoring device, the first hardware error detector further monitors whether an error occurs in the error notification frame transmitted by the first frame transmitting and receiving hardware unit, and causes the first frame transmitting and receiving hardware unit to transmit an anomaly notification frame for notifying of an occurrence of an anomaly in transmitting and receiving the error notification frame when detecting the occurrence of the error in the error notification frame, and in each of the one or more second error monitoring devices, when the second frame transmitting and receiving hardware unit has received the anomaly notification frame, the second hardware error detector regards, as the frame to be invalidated, a frame whose number of error detections or whose number of receptions held in the error state holder is greater than or equal to a predetermined number, and shifts the second error monitoring device to the invalidation mode. 6. The anti-fraud control system according to claim 1 , wherein the time-triggered communication protocol is a FlexRay protocol, and the error is any one of a synchronization (sync) error, a content error, a boundary violation, or a transmission (Tx) conflict defined by the FlexRay protocol. 7. The anti-fraud control system according to claim 6 , wherein the on-board network is based on a star topology including a star coupler to transmit and receive a frame to and from the branches via the star coupler, the error notification frame is a dynamic frame under the FlexRay protocol, and the first frame transmitting and receiving hardware unit determines a total number of cycles of transmitting the error notification frame in accordance with one of the branches connected to the first error monitoring device. 8. The anti-fraud control system according to claim 7 , wherein in the first error monitoring device, the first hardware error detector causes the first frame transmitting and receiving hardware unit to transmit a transition frame for invalidating one branch among the branches to prepare a period in which at least one of the one or more second error monitoring devices connected to the one branch shifts to the invalidation mode and others of the one or more second error monitoring devices connected to one or more of the branches other than the one branch do not shift to the invalidation mode, and detec

Assignees

Inventors

Classifications

  • Event detection, e.g. attack signature detection · CPC title

  • Frame classification, e.g. bad, good or erased (frame indication per se H04L1/0082) · CPC title

  • Star or tree networks · CPC title

  • Point-to-multipoint · CPC title

  • Proxies · CPC title

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Frequently asked questions

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What does patent US11909748B2 cover?
In an anti-fraud control system, a first error monitoring device includes a first frame transmitting and receiving unit that receives a frame flowing on the on-board network; and a first error detector that causes transmission of an error notification frame for notifying of an occurrence of an error in the frame when detecting the occurrence of the error in the frame received by the first frame…
Who is the assignee on this patent?
Panasonic Ip Corp America
What technology area does this patent fall under?
Primary CPC classification H04L63/1416. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 20 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).