Semiconductor integrated circuit and analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-11909413-B2
Application number	US-202117471887-A
Country	US
Kind code	B2
Filing date	Sep 10, 2021
Priority date	Mar 19, 2021
Publication date	Feb 20, 2024
Grant date	Feb 20, 2024

Abstract

A semiconductor integrated circuit has a digital signal generator that generates a binary signal whose logic transitions at a timing according to a discharge amount of a second wiring which is discharged when multiplication data of first data stored in a memory cell and second data on a first wiring is a first logic; and a transition timing detector that detects a timing at which the logic of the binary signal transitions.

First claim

The invention claimed is:

1. A semiconductor integrated circuit comprising:
a digital signal generator that generates a binary signal whose logic transitions at a timing according to a discharge amount of a second wiring which is discharged when multiplication data of first data stored in a memory cell and second data on a first wiring is a first logic; and
a transition timing detector that detects a timing at which the logic of the binary signal transitions.

2. The semiconductor integrated circuit according to claim 1 , wherein
the transition timing detector includes a plurality of arithmetic and logic units that compare the binary signal with a plurality of reference binary signals whose logics transition at timings according to different discharge amounts of the second wiring.

3. The semiconductor integrated circuit according to claim 2 , wherein
an output logic differs between the arithmetic and logic unit to which the reference binary signal whose logic transitions at a timing earlier than a timing at which the logic of the binary signal changes is input and the arithmetic and logic unit to which the reference binary signal whose logic transitions at a timing later than the timing at which the logic of the binary signal changes is input, among the plurality of arithmetic and logic units and the plurality of reference binary signals.

4. The semiconductor integrated circuit according to claim 3 , wherein
among the plurality of arithmetic and logic units and the plurality of reference binary signals, the arithmetic and logic unit to which the reference binary signal whose logic transitions at the timing earlier than the timing at which the logic of the binary signal changes is input outputs a signal of the first logic, and
the arithmetic and logic unit to which the reference binary signal whose logic transitions at the timing later than the timing at which the logic of the binary signal changes is input outputs a signal of a second logic.

5. The semiconductor integrated circuit according to claim 4 , further comprising:
a plurality of holders that hold a plurality of signals output from the plurality of arithmetic and logic units; and
an encoder that generates a digital signal according to a discharge amount of the second wiring using a number of the arithmetic and logic units each outputting the signal of the first logic and a number of the arithmetic and logic units each outputting the signal of the second logic at a predetermined timing based on the plurality of signals held by the plurality of holders.

6. The semiconductor integrated circuit according to claim 4 , further comprising:
a plurality of holders that hold a plurality of signals output from the plurality of arithmetic and logic units; and
an encoder that generates a digital signal according to a discharge amount of the second wiring depending on a timing at which outputs of the plurality of arithmetic and logic units change from the second logic to the first logic based on the plurality of signals held by the plurality of holders.

7. The semiconductor integrated circuit according to claim 2 , further comprising
a plurality of holders that hold a plurality of signals output from the plurality of arithmetic and logic units.

8. The semiconductor integrated circuit according to claim 7 , further comprising
an encoder that generates a digital signal according to a discharge amount of the second wiring based on the plurality of signals held by the plurality of holders.

9. The semiconductor integrated circuit according to claim 1 , wherein
the digital signal generator includes a logic inverter that causes a transition of the logic of the binary signal when a potential of the second wiring becomes equal to or lower than a predetermined threshold voltage.

10. The semiconductor integrated circuit according to claim 9 , wherein
the digital signal generator includes a pull-up circuit that pulls up the second wiring in a state before a transition of the output logic.

11. The semiconductor integrated circuit according to claim 10 , wherein
the digital signal generator includes a pull-up control circuit that releases the pull-up of the second wiring caused by the pull-up circuit when the output logic transitions.

12. The semiconductor integrated circuit according to claim 1 , further comprising:
a plurality of the memory cells arranged in a first direction and each storing the first data;
a plurality of the first wirings provided to correspond to the plurality of memory cells arranged in the first direction and supplying the second data to be multiplied by the first data; and
a second wiring pair provided to correspond to the plurality of memory cells arranged in the first direction and that includes one second wiring which is discharged when multiplication data of the first data, stored in each of the plurality of memory cells, and the second data, supplied by the first wiring corresponding to the memory cell, is the first logic; and another second wiring which is discharged when the multiplication data is a second logic.

13. The semiconductor integrated circuit according to claim 12 , wherein
the digital signal generator includes:
a first digital signal generator that generates a binary signal whose logic transitions at a timing according to a discharge amount of the one second wiring; and
a second digital signal generator that generates a binary signal whose logic transitions at a timing according to the discharge amount of the other second wiring.

14. The semiconductor integrated circuit according to claim 13 , wherein
the plurality of arithmetic and logic units that compare the binary signal generated by the first digital signal generator with the plurality of reference binary signals are provided separately from the plurality of arithmetic and logic units that compare the binary signal generated by the second digital signal generator with the plurality of reference binary signals.

15. The semiconductor integrated circuit according to claim 13 , further comprising
a reference signal generator that generates a plurality of reference binary signals, wherein
the plurality of reference binary signals generated by the reference signal generator are used for comparison with the binary signal generated by the first digital signal generator, and used for comparison with the binary signal generated by the second digital signal generator.

16. The semiconductor integrated circuit according to claim 15 , wherein
the reference signal generator generates the plurality of reference binary signals corresponding to different discharge amounts of the second wiring.

17. The semiconductor integrated circuit according to claim 15 , wherein
the reference signal generator includes:
a plurality of reference memory cells arranged in the first direction and each storing the first data;
a reference wiring pair provided to correspond to the plurality of reference memory cells arranged in the first direction, and that includes one reference wiring which is discharged when multiplication data of the first data, stored in each of the plurality of reference memory cells, and the second data, supplied by the first wiring corresponding to the reference memory cell, is the first logic; and another reference wiring which is discharged when the multiplication data is the second logic;
a first reference digital signal generator that generates a reference binary signal whose logic transitions at a timing according to a discharge amount of the one reference wiring; and
a second reference digital signal generator th

Assignees

• Kioxia Corp

Inventors

• Kawasumi Atsushi

Classifications

• H03M1/206 Primary

  using a logic interpolation circuit · CPC title

• G11C7/16

  Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters · CPC title

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G11C7/14 Primary

  Dummy cell management; Sense reference voltage generators · CPC title

• G11C11/54

  using elements simulating biological cells, e.g. neuron · CPC title