Method and system of dynamically controlling reset signal of IQ divider

Patent metadata

Field	Value
Publication number	US-11909407-B2
Application number	US-202217947845-A
Country	US
Kind code	B2
Filing date	Sep 19, 2022
Priority date	Jun 17, 2022
Publication date	Feb 20, 2024
Grant date	Feb 20, 2024

Abstract

A system and method to dynamically control a reset signal for an IQ divider are provided. The system includes an IQ divider configured to output a IQ divider output clock; an input configured to receive a reference clock; a failure sensing circuit configured to sense a failure in the IQ divider output clock, the failure sensing circuit including an automatic frequency calibration (AFC) logic; and a control circuit configured to control a reset signal provided to the IQ divider, based on an output of the failure sensing circuit corresponding the failure sensed by the failure sensing circuit.

First claim

What is claimed is:

1. A system comprising:
an IQ divider configured to output a IQ divider output clock;
an input configured to receive a reference clock;
a failure sensing circuit configured to sense a failure in the IQ divider output clock, the failure sensing circuit comprising an automatic frequency calibration (AFC) logic; and
a control circuit configured to control a reset signal provided to the IQ divider, based on an output of the failure sensing circuit corresponding the failure sensed by the failure sensing circuit.

2. The system of claim 1 , wherein the control circuit comprises:
a counter,
a delay control element,
a multiplexer, and
a variable delay element.

3. The system as claimed in claim 2 , wherein the failure sensing circuit is further configured to check an output frequency of the IQ divider output clock with respect to a frequency of the reference clock.

4. The system as claimed in claim 3 , wherein the failure sensing circuit further comprises an internal counter that is triggered based on the IQ divider output clock.

5. The system as claimed in claim 4 , wherein the failure sensing circuit is further configured to sense the failure by determining a presence of the IQ divider output clock based on a frequency measurement using the counter, wherein the counter is incremented by the IQ divider output clock.

6. The system as claimed in claim 2 , wherein the control circuit is further configured to determine a failure scenario based on an output of the AFC logic.

7. The system as claimed in claim 6 , wherein the control circuit is further configured to control the reset signal based on the failure scenario.

8. The system as claimed in claim 6 , wherein the failure scenario comprises one of:
a) a first ratio of a first frequency of an input clock to the IQ divider and a second frequency of the reference clock being a first integer;
b) a second ratio of the first frequency of the input clock and the second frequency of the reference clock is a first non-integer number, wherein a first fractional portion of the second ratio being less than a latch-up window threshold, wherein the latch-up window threshold is determined as t latchup /N, and wherein N is a number of reference cycles allowed to pass before activating the delay control element; or
c) a third ratio of the first frequency of the input clock and the second frequency of the reference clock being a second non-integer number, wherein a second fractional portion of the third ratio is greater than the latch-up window threshold.

9. The system as claimed in claim 8 , wherein the control circuit is further configured to use a delay control function for the failure scenario corresponding to each of:
a) the first ratio is the first integer, and
b) the second ratio wherein the first fractional portion is less than the latch-up window threshold.

10. The system as claimed in claim 2 , wherein the control circuit is further configured to:
reassert the reset signal asynchronously in the IQ divider to restore an initial condition of the IQ divider;
deassert the reset signal on a next positive edge of the reference clock; and
position the reset signal with respect to an input clock of the IQ divider based on a failure scenario.

11. A method of dynamically controlling a reset signal for an IQ divider by a system, the method comprising:
monitoring an output frequency of the IQ divider with respect to an input reference clock frequency of a reference clock;
detecting a failure in the IQ divider based on the monitored output frequency of the IQ divider; and
dynamically controlling, the reset signal based on the detected failure.

12. The method as claimed in claim 11 , wherein dynamically controlling reset signal comprises:
reasserting the reset signal asynchronously in the IQ divider to restore an initial condition of the IQ divider;
deasserting the reset signal on a next positive edge of the reference clock;
determining a failure scenario associated with the failure; and
position the reset signal with respect to an input clock of the IQ divider based on the failure scenario.

13. The method as claimed in claim 12 , wherein the system comprises:
the IQ divider;
an input configured to receive the reference clock;
a failure sensing circuit configured to sense the failure, the failure sensing circuit comprising an AFC logic; and
a control circuit configured to control the reset signal based on the control circuit, comprising:
a counter,
a delay control element,
a multiplexer, and

a variable delay element.

14. An apparatus comprising:
a memory storing one or more instructions; and
a processor for executing one or more instructions stored in the memory;
wherein the processor is configured to implement:
an IQ divider configured to output a IQ divider output clock;
an input configured to receive a reference clock;
a failure sensing circuit configured to sense a failure in the IQ divider output clock, the failure sensing circuit comprising an automatic frequency calibration (AFC) logic; and
a control circuit configured to control a reset signal provided to the IQ divider, based on an output of the failure sensing circuit corresponding the failure sensed by the failure sensing circuit.

15. The apparatus of claim 14 , wherein the control circuit comprises:
a counter,
a delay control element,
a multiplexer, and
a variable delay element.

16. The apparatus as claimed in claim 15 , wherein the failure sensing circuit is further configured to check an output frequency of the IQ divider output clock with respect to a frequency of the reference clock.

17. The apparatus as claimed in claim 16 , wherein the failure sensing circuit further comprises an internal counter that is triggered based on the IQ divider output clock.

18. The apparatus as claimed in claim 17 , wherein the failure sensing circuit is further configured to sense the failure by determining a presence of the IQ divider output clock based on a frequency measurement using the counter, wherein the counter is incremented by the IQ divider output clock.

19. The apparatus as claimed in claim 16 , wherein the control circuit is further configured to:
reassert the reset signal asynchronously in the IQ divider to restore an initial condition of the IQ divider;
deassert the reset signal on a next positive edge of the reference clock; and
position the reset signal with respect to an input clock of the IQ divider based on a failure scenario.

20. The apparatus as claimed in claim 15 , wherein the control circuit is further configured to determine a failure scenario based on an output of the AFC logic.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Rathee Praveen
• Kalyanamahadevi Gopalan Jawarlal Vishnu
• Ghosh Sanjeeb Kumar
• Verma Avneesh Singh

Classifications

• H03L7/193 Primary

  the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider · CPC title

• H03K5/135

  by the use of time reference signals, e.g. clock signals · CPC title

• H03K21/08 Primary

  Output circuits · CPC title

• H03L7/148

  said digital means comprising a counter or a divider · CPC title