Thin film transistor array substrate having metal layer bridging structure and display panel including the same

Patent metadata

Field	Value
Publication number	US-11908870-B2
Application number	US-201916957392-A
Country	US
Kind code	B2
Filing date	Oct 22, 2019
Priority date	Jul 18, 2019
Publication date	Feb 20, 2024
Grant date	Feb 20, 2024

Abstract

A TFT array substrate includes a substrate layer and a metal layer disposed on the substrate layer. The metal layer includes a metal layer bridging structure having a first metal layer and a bridging second metal layer. An insulating layer is disposed between the first metal layer and the bridging second metal layer. The first metal layer includes two segments of a first segment and a second segment of the first metal layer, which are disposed at intervals. The first segment and the second segment of the first metal layer are connected by the bridging second metal layer. The TFT array substrate has a bending region adopting a new metal layer routing structure, and routing of the first metal layer in the bending region is prevented from passing through two holes of a filling layer (OILD), thereby effectively reducing the risk of subsequent breakage due to over-etching.

First claim

What is claimed is:

1. A thin film transistor (TFT) array substrate, comprising a substrate layer and a metal layer disposed on the substrate layer, wherein the metal layer comprises a metal layer bridging structure, the metal layer bridging structure comprises a first metal layer and a bridging metal layer, and an insulating layer is disposed between the first metal layer and the bridging metal layer;
wherein the first metal layer comprises two segments of a first segment of the first metal layer and a second segment of the first metal layer, the first segment of the first metal layer and the second segment of the first metal layer are disposed at intervals, and the bridging metal layer connects the first segment of the first metal layer and the second segment of the first metal layer;
wherein the TFT array substrate comprises a display region and a bending region, and the metal layer bridging structure is disposed in the bending region; and wherein in the bending region, the TFT array substrate further comprises:
a gate layer disposed on the substrate layer;
an interlayer dielectric layer disposed on a side of the gate layer away from the substrate layer;
an organic filling layer disposed on the interlayer dielectric layer, wherein the organic filling layer is provided with a plurality of first through-holes and a plurality of second through-holes; wherein the first segment of the first metal layer is disposed in each of the first through-holes, and the second segment of the first metal layer is disposed on the organic filling layer and located outside of the first through-holes; the insulating layer is disposed on the first metal layer, and the bridging metal layer is disposed on a side of the insulating layer away from the first metal layer; and
wherein the bridging metal layer is disposed between adjacent ones of the second through-holes.

2. The TFT array substrate according to claim 1 , wherein the substrate layer in the display region is provided with a TFT device functional layer, and the metal layer comprises a first gate layer, a second gate layer, and a first metal layer of the TFT device functional layer.

3. The TFT array substrate according to claim 2 , wherein the metal layer in the display region further comprises a second metal layer, and the second metal layer is electrically connected to the first metal layer through a via hole.

4. The TFT array substrate according to claim 3 , wherein the metal layer in the display region further comprises an anode metal layer, and the anode metal layer is electrically connected to the second metal layer through the via hole.

5. The TFT array substrate according to claim 1 , wherein the gate layer comprises a first gate layer and a second gate layer disposed on the first gate layer away from the substrate layer; and
wherein the first segment of the first metal layer is electrically connected to the second gate layer through a via hole.

6. The TFT array substrate according to claim 1 , wherein the gate layer comprises a first gate layer and a second gate layer disposed on the first gate layer away from the substrate layer; and the TFT array substrate further comprises:
a first transferring metal layer disposed in each of the second through-holes, disposed at a same layer as the first segment of the first metal layer, and electrically connected to the first gate layer through a via hole; and
a second transferring metal layer disposed at a same layer as the bridging metal layer, and electrically connected to the first gate layer through the first transferring metal layer.

7. The TFT array substrate according to claim 1 , wherein the gate layer comprises a first gate layer and a second gate layer disposed on the first gate layer away from the substrate layer; and wherein the first segment of the first metal layer is electrically connected to the second gate layer through a via hole; and
wherein the TFT array substrate further comprises:
a first transferring metal layer disposed in each of the second through-holes, disposed at a same layer as the first segment of the first metal layer, and electrically connected to the first gate layer through a via hole; and
a second transferring metal layer disposed at a same layer as the bridging metal layer, and electrically connected to the first gate layer through the first transferring metal layer.

8. A display panel comprising a TFT array substrate, wherein the TFT array substrate comprises a substrate layer and a metal layer disposed on the substrate layer, wherein the metal layer comprises a metal layer bridging structure, the metal layer bridging structure comprises a first metal layer and a bridging metal layer, and an insulating layer is disposed between the first metal layer and the bridging metal layer;
wherein the first metal layer comprises two segments of a first segment of the first metal layer and a second segment of the first metal layer, the first segment of the first metal layer and the second segment of the first metal layer are disposed at intervals, and the bridging metal layer connects the first segment of the first metal layer and the second segment of the first metal layer;
wherein the TFT array substrate comprises a display region and a bending region, and the metal layer bridging structure is disposed in the bending region; and wherein in the bending region, the TFT array substrate further comprises:
a gate layer disposed on the substrate layer;
an interlayer dielectric layer disposed on a side of the gate layer away from the substrate layer;
an organic filling layer disposed on the interlayer dielectric layer, wherein the organic filling layer is provided with a plurality of first through-holes and a plurality of second through-holes; wherein the first segment of the first metal layer is disposed in each of the first through-holes, and the second segment of the first metal layer is disposed on the organic filling layer and located outside of the first through-holes; the insulating layer is disposed on the first metal layer, and the bridging metal layer is disposed on a side of the insulating layer away from the first metal layer; and
wherein the bridging metal layer is disposed between adjacent ones of the second through-holes.

9. The display panel according to claim 8 , wherein the display panel is a flexible active matrix organic light emitting diode (AMOLED) display panel.

10. The display panel according to claim 8 , wherein the gate layer comprises a first gate layer and a second gate layer disposed on the first gate layer away from the substrate layer; and
wherein the first segment of the first metal layer is electrically connected to the second gate layer through a via hole.

11. The display panel according to claim 8 , wherein the gate layer comprises a first gate layer and a second gate layer disposed on the first gate layer away from the substrate layer; and the TFT array substrate further comprises:
a first transferring metal layer disposed in each of the second through-holes, disposed at a same layer as the first segment of the first metal layer, and electrically connected to the first gate layer through a via hole; and
a second transferring metal layer disposed at a same layer as the bridging metal layer, and electrically connected to the first gate layer through the first transferring metal layer.

12. The display panel according to claim 8 , wherein the gate layer comprises a first gate layer and a second gate layer disposed on the first gate layer away from the substrate layer; and wherein the first segment of the first metal layer is electrically connected to the second gate layer through a via hole; and
wherein the TFT array substrat

Assignees

• Wuhan China Star Optoelectronics Semiconductor Display Tech Co Ltd

Inventors

• Ming Xing
• Cao Zhongtao

Classifications

• H10D86/411

  characterised by materials, geometry or structure of the substrates · CPC title

• H10D86/443 Primary

  adapted for preventing breakage, peeling or short circuiting · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• H01L27/1218 Primary

  Electricity · mapped topic

• H10K59/123

  Connection of the pixel electrodes to the thin film transistors [TFT] · CPC title