Semiconductor device including well region

Patent metadata

Field	Value
Publication number	US-11908807-B2
Application number	US-202217574212-A
Country	US
Kind code	B2
Filing date	Jan 12, 2022
Priority date	Jun 14, 2021
Publication date	Feb 20, 2024
Grant date	Feb 20, 2024

Abstract

A semiconductor device is provided. The semiconductor device includes: a substrate with first-conductivity-type impurities; first and second active regions provided on the substrate; a first deep element isolation layer surrounding the first active region; a second deep element isolation layer surrounding the second active region; a suction region surrounding the first and second deep element isolation layers, the suction region including the first-conductivity-type impurities; a well region provided in the substrate between the first and second active regions, the well region including second-conductivity-type impurities different from the first-conductivity-type impurities; a shallow element isolation layer provided between the suction region and the well region; and a guard structure connected to the suction region. The substrate includes a signal path portion that is provided between a top surface of the substrate and the well region, and surrounds an upper portion of the well region.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate comprising first-conductivity-type impurities;
a first active region and a second active region provided on the substrate;
a first deep element isolation layer surrounding the first active region;
a second deep element isolation layer surrounding the second active region;
a suction region surrounding the first deep element isolation layer and the second deep element isolation layer, the suction region comprising the first-conductivity-type impurities;
a well region provided in the substrate between the first active region and the second active region, the well region comprising second-conductivity-type impurities different from the first-conductivity-type impurities;
a shallow element isolation layer provided between the suction region and the well region; and
a guard structure connected to the suction region,
wherein the substrate comprises a signal path portion that is provided between a top surface of the substrate and the well region, and surrounds an upper portion of the well region.

2. The semiconductor device according to claim 1 , wherein the signal path portion comprises a first path portion and a second path portion, wherein the first path portion is provided above an upper surface of the well region, and the second path portion provided below the upper surface of the well region.

3. The semiconductor device according to claim 2 , wherein:
the well region is spaced apart from the shallow element isolation layer; and
the second path portion is provided between the well region and the shallow element isolation layer.

4. The semiconductor device according to claim 1 , wherein:
the well region is spaced apart from the shallow element isolation layer; and
a minimum distance between the shallow element isolation layer and the well region is smaller than a maximum width of the shallow element isolation layer along a first direction parallel to the top surface of the substrate.

5. The semiconductor device according to claim 1 , wherein a minimum distance between the top surface of the substrate corresponding to the signal path portion and an upper surface of the well region is smaller than a maximum width of the shallow element isolation layer along a first direction parallel to the top surface of the substrate.

6. The semiconductor device according to claim 1 , wherein a concentration of the first-conductivity-type impurities in the suction region is higher than a concentration of the first-conductivity-type impurities in the substrate.

7. The semiconductor device according to claim 1 , wherein:
the guard structure comprises first guard vias and second guard vias provided on the suction region, and a first guard line provided on both the first guard vias and the second guard vias; and
an outer longer side wall of one of the first guard vias faces inner longer side walls of two of the second guard vias.

8. The semiconductor device according to claim 1 , wherein:
the well region comprises a plurality of well regions; and
the suction region comprises a plurality of suction regions provided between two of the plurality of well regions that are adjacent to each other.

9. A semiconductor device comprising:
a substrate comprising first-conductivity-type impurities;
a first active region and a second active region provided on the substrate;
a suction region surrounding the first active region and the second active region, the suction region comprising the first-conductivity-type impurities; and
a well region provided in the substrate between the first active region and the second active region, the well region comprising second-conductivity-type impurities different from the first-conductivity-type impurities,
wherein the well region is spaced apart from a top surface of the substrate and the suction region, and
wherein a minimum distance between the well region and the top surface of the substrate is smaller than a width of the suction region along a first direction parallel to the top surface of the substrate.

10. The semiconductor device according to claim 9 , wherein:
the substrate comprises a first path portion provided between the top surface of the substrate and the well region; and
the first path portion comprises the first-conductivity-type impurities.

11. The semiconductor device according to claim 10 , wherein the first path portion covers an uppermost portion of the well region that faces the top surface of the substrate.

12. The semiconductor device according to claim 9 , further comprising:
a guard structure connected to the suction region.

13. The semiconductor device according to claim 12 , wherein the guard structure is connected to a ground node.

14. The semiconductor device according to claim 9 , further comprising:
a shallow element isolation layer provided between the suction region and the well region.

15. The semiconductor device according to claim 14 , wherein the substrate comprises a first path portion and a second path portion, wherein the first path portion is provided between the top surface of the substrate and the well region, and the second path portion is provided between the shallow element isolation layer and the well region.

16. The semiconductor device according to claim 14 , wherein a minimum distance between the well region and the shallow element isolation layer is smaller than the width of the suction region.

17. A semiconductor device comprising:
a substrate comprising first-conductivity-type impurities;
an active region provided on the substrate;
a suction region surrounding the active region and comprising the first-conductivity-type impurities; and
a guard structure connected to the suction region,
wherein the guard structure comprises first guard vias and second guard vias provided on the suction region, and a first guard line provided on the first guard vias and the second guard vias, and
wherein an outer longer side wall of one of the first guard vias faces inner longer side walls of two of the second guard vias.

18. The semiconductor device according to claim 17 , wherein the guard structure is connected to a ground node.

19. The semiconductor device according to claim 17 , wherein shorter side walls of two of the first guard vias face each other.

20. The semiconductor device according to claim 17 , further comprising:
a well region provided in the substrate,
wherein the well region comprises second-conductivity-type impurities different from the first-conductivity-type impurities.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Shin Huichul
• Lee Hyungjin
• Park Jinhong
• Song Mingeun
• Jeong Euiyoung
• Fujii Hiroki

Classifications

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10W42/00

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H10W42/20 Primary

  protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• H10D84/0191

  Manufacturing their doped wells · CPC title