Charge detection circuit and detection method thereof and display panel

Patent metadata

Field	Value
Publication number	US-11908360-B2
Application number	US-202117440741-A
Country	US
Kind code	B2
Filing date	Jun 4, 2021
Priority date	Apr 8, 2021
Publication date	Feb 20, 2024
Grant date	Feb 20, 2024

Abstract

A charge detection circuit and a detection method thereof and a display panel are provided. A second storage capacitor is added to the charge detection circuit. The second storage capacitor can continuously accumulate the charge amount of a second thin film transistor. When a third thin film transistor is turned on, all the charges accumulated by the second storage capacitor flow into an integrator, so that second thin film transistor does not need to be operated in a linear region. Increasing the charge amount of the charge detection circuit is beneficial for the display panel to distinguish light sensor signals.

First claim

What is claimed is:

1. A charge detection circuit, comprising: a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a first storage capacitor, and a second storage capacitor;
a gate electrode of the first thin film transistor electrically connected to a first power signal, a drain electrode of the first thin film transistor electrically connected to a second power signal, and a source electrode of the first thin film transistor electrically connected to a first node;
a gate electrode of the second thin film transistor electrically connected to the first node, a drain electrode of the second thin film transistor electrically connected to a third power signal, and a source electrode of the second thin film transistor electrically connected to a second node;
a gate electrode of the third thin film transistor electrically connected to a first control signal, a drain electrode of the third thin film transistor electrically connected to the second node, and a source electrode of the third thin film transistor electrically connected to an input terminal of an integrator;
a gate electrode of the fourth thin film transistor electrically connected to a second control signal, a drain electrode of the fourth thin film transistor electrically connected to a fourth power signal, and a source electrode of the fourth thin film transistor electrically connected to the first node;
one terminal of the first storage capacitor electrically connected to the gate electrode of the first thin film transistor, and the other terminal of the first storage capacitor electrically connected to the first node; and
one terminal of the second storage capacitor electrically connected to the drain electrode of the fourth thin film transistor, and the other terminal of the second storage capacitor electrically connected to the second node,
wherein a difference value between a voltage at the gate electrode of the first thin film transistor and a voltage at the source electrode is ranged from 5 volts to 10 volts.

2. The charge detection circuit of claim 1 , wherein a combination of the first power signal, the second power signal, the third power signal, the fourth power signal, the first control signal, and the second control signal sequentially corresponds to an initial stage, a photocurrent amplifying stage, a photocurrent obtaining stage, and a reset stage.

3. The charge detection circuit of claim 2 , wherein the first power signal, the second power signal, the third power signal, and the fourth power signal are all fixed direct-current voltages, and amplitudes of the first power signal, the second power signal, the third power signal, and the fourth power signal are ranged from −10 volts to 20 volts.

4. The charge detection circuit of claim 2 , wherein in the photocurrent obtaining stage, the first control signal is at a high voltage level, and the second control signal is at a low voltage level.

5. The charge detection circuit of claim 2 , wherein in the reset stage, the first control signal is at a low voltage level, and the second control signal is at a high voltage level.

6. The charge detection circuit of claim 2 , wherein in the initial stage, the first control signal is at a low voltage level, and the second control signal is at a low voltage level.

7. The charge detection circuit of claim 2 , wherein in the photocurrent amplifying stage, the first control signal is at a low voltage level, and the second control signal is at a low voltage level.

8. The charge detection circuit of claim 1 , wherein the first thin film transistor, the second thin film transistor, the third thin film transistor, and the fourth thin film transistor are all low temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon thin film transistors.

9. A display panel, comprising a charge detection circuit, the charge detection circuit comprising: a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a first storage capacitor, and a second storage capacitor;
a gate electrode of the first thin film transistor electrically connected to a first power signal, a drain electrode of the first thin film transistor electrically connected to a second power signal, and a source electrode of the first thin film transistor electrically connected to a first node;
a gate electrode of the second thin film transistor electrically connected to the first node, a drain electrode of the second thin film transistor electrically connected to a third power signal, and a source electrode of the second thin film transistor electrically connected to a second node;
a gate electrode of the third thin film transistor electrically connected to a first control signal, a drain electrode of the third thin film transistor electrically connected to the second node, and a source electrode of the third thin film transistor electrically connected to an input terminal of an integrator;
a gate electrode of the fourth thin film transistor electrically connected to a second control signal, a drain electrode of the fourth thin film transistor electrically connected to a fourth power signal, and a source electrode of the fourth thin film transistor electrically connected to the first node;
one terminal of the first storage capacitor electrically connected to the gate electrode of the first thin film transistor, and the other terminal of the first storage capacitor electrically connected to the first node; and
one terminal of the second storage capacitor electrically connected to the drain electrode of the fourth thin film transistor, and the other terminal of the second storage capacitor electrically connected to the second node,
wherein a difference value between a voltage at the gate electrode of the first thin film transistor and a voltage at the source electrode is ranged from 5 volts to 10 volts.

10. The display panel of claim 9 , wherein a combination of the first power signal, the second power signal, the third power signal, the fourth power signal, the first control signal, and the second control signal sequentially corresponds to an initial stage, a photocurrent amplifying stage, a photocurrent obtaining stage, and a reset stage.

11. The display panel of claim 10 , wherein the first power signal, the second power signal, the third power signal, and the fourth power signal are all fixed direct-current voltages, and amplitudes of the first power signal, the second power signal, the third power signal, and the fourth power signal are ranged from −10 volts to 20 volts.

12. The display panel of claim 10 , wherein in the photocurrent obtaining stage, the first control signal is at a high voltage level, and the second control signal is at a low voltage level.

13. The display panel of claim 10 , wherein in the reset stage, the first control signal is at a low voltage level, and the second control signal is at a high voltage level.

14. The display panel of claim 10 , wherein in the initial stage, the first control signal is at a low voltage level, and the second control signal is at a low voltage level.

15. The display panel of claim 10 , wherein in the photocurrent amplifying stage, the first control signal is at a low voltage level, and the second control signal is at a low voltage level.

16. The display panel of claim 9 , wherein the first thin film transistor, the second thin film transistor, the third thin film transistor, and the fourth thin film transistor are all low temperature polysilicon thin film tran

Assignees

• Shenzhen China Star Optoelectronics Semiconductor Display Tech Co Ltd

Inventors

• Wu Sijia
• Zhang Xin
• Yao Jiangbo
• Wang Haijun

Classifications

• G09G3/006 Primary

  Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays (testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309) · CPC title

• G09G2330/08

  Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared · CPC title

• G09G2330/12

  Test circuits or failure detection circuits included in a display system, as permanent part thereof · CPC title

• H10K59/60 Primary

  OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes · CPC title

• G09G2360/14

  Detecting light within display terminals, e.g. using a single or a plurality of photosensors · CPC title