Method, device, and electronic apparatus of inspecting display panel

Patent metadata

Field	Value
Publication number	US-11907626-B2
Application number	US-202016969566-A
Country	US
Kind code	B2
Filing date	May 13, 2020
Priority date	Apr 27, 2020
Publication date	Feb 20, 2024
Grant date	Feb 20, 2024

Abstract

A method, a device, and an electronic apparatus are provided. When a user performs the design operation in a display panel design program, the method includes steps of collecting display panel design parameters corresponding to a design operation of the user in the display panel design program obtaining a design strategy preset in the display panel; checking if the display panel design parameters are normal based upon the design strategy of the display panel; and alerting in the display panel design program when the display panel design parameters are abnormal.

First claim

What is claimed is:

1. A method of inspecting a display panel, comprising:
collecting display panel design parameters corresponding to a design operation of a user in a display panel design program when the user performs the design operation in the display panel design program;
obtaining a design strategy preset for the display panel, wherein the design strategy comprises a design strategy of each of one or more structures in the display panel, and a correspondence between the structures in the display panel;
checking if the display panel design parameters are normal based upon the design strategy of the display panel; and
alerting in the display panel design program when the display panel design parameters are abnormal,
wherein the display panel is a thin film transistor (TFT) liquid crystal display panel, and the design strategy comprises a TFT substrate design strategy, an upper polarizer design strategy, a color filter (CF) substrate design strategy, and a lower polarizer design strategy;
the TFT substrate design strategy comprises specification design parameters of each of layers of a TFT substrate, and a correspondence between the layers of the TFT substrate; and
the CF substrate design strategy comprises specification design parameters of each of layers of a CF substrate, and a correspondence between the layers of the CF substrate.

2. The method according to claim 1 , wherein the collecting of the display panel design parameters comprises:
when the user performs the design operation in the display panel design program, collecting design parameters of an operation target corresponding to the design operation; and
collecting a correspondence between the operation target and existing design objects;
wherein the display panel design parameters corresponding to the design operation of the user comprises the design parameters of the operation target, and the correspondence between the operation target and the existing design objects.

3. The method according to claim 1 , wherein the TFT substrate design strategy comprises a test terminal design strategy, and the test terminal design strategy comprises a test terminal size specification, and that a distance between a test terminal and a driving chip is greater than a preset threshold, a distance between the test terminal and a long side of the TFT substrate is greater than X, a distance between the test terminal and a short side of the TFT substrate is greater than Y, and a spacing between test terminals is greater than Z, where X, Y, and Z are positive.

4. The method according to claim 3 , wherein the TFT substrate design strategy further comprises a strategy of material and thickness, a strategy of line width definition and limitation, a strategy of alignment error limitation, and a strategy of TFT process parameters.

5. The method according to claim 4 , wherein the strategy of material and thickness comprises information of material and thickness of at least one of a gate electrode, a gate insulating layer, a semiconductor layer, a doped semiconductor layer, a source-drain metal, or a transparent electrode.

6. The method according to claim 4 , wherein the strategy of line width definition and limitation comprises information of line width definition and limitation of at least one of a gate metal line, a semiconductor layer line, a source-drain metal line, a contact hole, or an ITO transparent electrode.

7. The method according to claim 4 , wherein the strategy of alignment error limitation comprises information of at least one of alignment error limitation between a semiconductor layer and a gate metal, alignment error limitation between a source-drain metal and the gate metal, alignment error limitation between the source-drain metal and the semiconductor layer, alignment error limitation between a contact hole and the gate metal, alignment error limitation between the contact hole and the source-drain metal, alignment error limitation between a transparent electrode and the source-drain metal, alignment error limitation between the transparent electrode and the gate metal, or alignment error limitation between the transparent electrode and the contact hole.

8. The method according to claim 4 , wherein the strategy of TFT process parameters comprises at least one of an electron mobility, a cut-off voltage, a leakage current, or a parasitic capacitance.

9. The method according to claim 1 , further comprising:
obtaining a new design strategy of the display panel, wherein the new design strategy comprises a design strategy of at least one of the structures in the display panel, or a correspondence between at least two of the structures in the display panel; and
updating the design strategy of the display panel based on the new design strategy.

10. A device for inspecting a display panel, comprising:
a collecting module for collecting display panel design parameters corresponding to a design operation of a user in a display panel design program when the user performs the design operation in the display panel design program;
an obtaining module for obtaining a design strategy preset for the display panel, wherein the design strategy comprises a design strategy of each of one or more structures in the display panel, and a correspondence between the structures in the display panel;
a checking module for checking if the display panel design parameters are normal based upon the design strategy of the display panel; and
an alerting module for alerting in the display panel design program when the display panel design parameters are abnormal,
wherein the display panel is a thin film transistor (TFT) liquid crystal display panel, and the design strategy comprises a TFT substrate design strategy, an upper polarizer design strategy, a color filter (CF) substrate design strategy, and a lower polarizer design strategy;
the TFT substrate design strategy comprises specification design parameters of each of layers of a TFT substrate, and a correspondence between the layers of the TFT substrate; and
the CF substrate design strategy comprises specification design parameters of each of layers of a CF substrate, and a correspondence between the layers of the CF substrate.

11. The device according to claim 10 , wherein the collecting module is specifically used for:
collecting design parameters of an operation target corresponding to the design operation when the user performs the design operation in the display panel design program; and
collecting a correspondence between the operation target and existing design objects;
wherein the display panel design parameters corresponding to the design operation performed by the user comprises the design parameters of the operation target, and a correspondence between the operation target and the existing design objects.

12. The device according to claim 10 , wherein the TFT substrate design strategy comprises a test terminal design strategy, wherein the test terminal design strategy comprises a test terminal size specification, and that a distance between a test terminal and a driving chip is greater than a preset threshold, a distance between the test terminal and a long side of the TFT substrate is greater than X, a distance between the test terminal and a short side of the TFT substrate is greater than Y, and a spacing between test terminals is greater than Z, where X, Y, and Z are positive.

13. The device according to claim 10 , wherein the TFT substrate design strategy further comprises a strategy of material and thickness, a strategy of line width definition and limitation, a strategy of alignment error limitation, and a strategy of TFT process parameters.

Assignees

• Shenzhen China Star Optoelectronics Semiconductor Display Tech Co Ltd

Inventors

• Lv Bo
• Wang zui

Classifications

• G06F30/31 Primary

  Design entry, e.g. editors specifically adapted for circuit design · CPC title

• G09G3/006 Primary

  Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays (testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309) · CPC title

• G02F1/1309 Primary

  Repairing; Testing · CPC title