Serial interface for semiconductor package

Patent metadata

Field	Value
Publication number	US-11907140-B2
Application number	US-202217699942-A
Country	US
Kind code	B2
Filing date	Mar 21, 2022
Priority date	Aug 3, 2018
Publication date	Feb 20, 2024
Grant date	Feb 20, 2024

Abstract

A system for serial communication includes a controller, a semiconductor package comprising a plurality of semiconductor die, and a serial interface configured to connect the plurality of semiconductor die to the controller. The serial interface includes a controller-to-package connection and a package-to-controller connection, and the serial interface is configured to employ a signaling protocol using differential data signaling with no separate clock signals.

First claim

What is claimed is:

1. A system for serial communication, comprising:
a controller;
a semiconductor package comprising a semiconductor memory; and
a serial interface configured to connect the semiconductor memory to the controller,
wherein the serial interface is configured to transfer data between the controller and the semiconductor memory at a speed of transfer that is variable by employing a signaling protocol, and
wherein the serial interface is configured to transfer the data together with an encoded clock signal, the encoded clock signal having a rate associated with the variable speed of transfer of data, wherein the encoded clock signal is embedded together with the data in a transmitted signal.

2. The system of claim 1 , wherein the speed of transfer of the data is communicated by the controller to the semiconductor memory using the serial interface and the signaling protocol.

3. The system of claim 2 , wherein the serial interface is configured to implement a plurality of lanes using four pins per lane, and one of the plurality of lanes comprises the controller-to-package connection and the package-to-controller connection.

4. The system of claim 1 , wherein the serial interface comprises a controller-to-package connection and a package-to-controller connection.

5. The system of claim 1 , wherein the signaling protocol is one of LVDS and CML.

6. The system of claim 1 , wherein the controller is configured to selectively set the rate of the encoded clock signal to minimize power consumption.

7. The system of claim 1 , wherein the serial interface comprises a bridge device configured to serially connect to the controller, and wherein the semiconductor memory comprises a plurality of semiconductor die, and wherein the bride device is configured to connect to the plurality of semiconductor die in parallel, via at least one parallel bus connection.

8. The system of claim 7 , wherein the bridge device is configured to implement an error correction technique.

9. The system of claim 8 , wherein the bridge device is configured to reprogram the error correction technique based on instructions received from the controller.

10. The system of claim 7 , wherein the serial interface is included in the semiconductor package, and the semiconductor package comprises an encapsulation material that encapsulates the plurality of semiconductor die and encapsulates the bridge device.

11. The system of claim 7 , wherein the semiconductor package comprises an encapsulation material that encapsulates the plurality of semiconductor die, and the bridge device is disposed outside of the encapsulation material.

12. The system of claim 7 , wherein the serial interface includes:
a controller-to-package connection comprising a first pin and a second pin connected to the controller, and the controller-to-package connection is configured to transmit a differential signal to the controller using the first pin and the second pin; and
a package-to-controller connection comprising a third pin and a fourth pin connected to the controller, and the package-to-controller connection is configured to receive a differential signal from the controller using the third pin and the fourth pin.

13. The system of claim 1 , wherein the semiconductor memory comprises a plurality of semiconductor die, the system further comprising a plurality of serial interfaces including the serial interface, the plurality of serial interfaces respectively connecting the plurality of semiconductor die to the controller.

14. A semiconductor package, comprising:
a flash memory; and
a bridge device comprising a high-speed serial interface connected to an external controller and a parallel interface connected to the flash memory,
wherein the high-speed serial interface is configured to transfer data between the external controller and the flash memory at a speed of transfer that is variable by employing a signaling protocol, and
wherein the high-speed serial interface is configured to transfer the data together with an encoded clock signal, the encoded clock signal having a rate associated with the variable speed of transfer of data, wherein the encoded clock signal is embedded together with the data in a transmitted signal.

15. The semiconductor package of claim 14 , wherein the bridge device is configured to implement an error correction technique according to error correction firmware accessible to the bridge device.

16. The semiconductor package of claim 15 , wherein the bridge device is configured to reprogram the error correction firmware based on instructions received from the controller.

17. The semiconductor package of claim 14 , wherein the bridge device comprises a controller configured to determine a device identification included in a first communication received via the high-speed serial interface, and configured to responsively transmit, based on the device identification, a second communication to the flash memory via the parallel interface.

18. A method for communication for a semiconductor package comprising a package controller, a serial interface, and a parallel interface, the method comprising:
receiving, by the serial interface from an external controller, a first communication comprising device identity information, the first communication configured to transfer data between the external controller and the semiconductor package at a speed of transfer that is variable according to a signaling protocol, wherein the serial interface is configured to transfer the data together with an encoded clock signal, the encoded clock signal having a rate associated with the variable speed of transfer of data, wherein the encoded clock signal is embedded together with the data in a transmitted signal;
identifying, by the package controller, a first semiconductor die based on the device identity information;
routing, by the package controller, a second communication to the first semiconductor die via the parallel interface;
receiving, by the package controller from the first semiconductor die, via the parallel interface, a third communication; and
transmitting, by the package controller to the external controller via the serial interface using the signaling protocol that includes the encoded clock signal, a fourth communication based on the third communication.

19. The method of claim 18 , wherein the first communication is a command to perform an operation, and wherein the third communication indicates that the operation was implemented.

20. The method of claim 19 , wherein the device identity information of the first communication specifies the first semiconductor die and a second semiconductor die, and further comprising:
receiving, by the package controller from the second semiconductor die, via the parallel interface, a fifth communication; and
transmitting, by the package controller to the external controller via the serial interface, a sixth communication based on the fifth communication.

21. The method of claim 20 , wherein the sixth communication is transmitted asynchronously with the fourth communication.

22. The method of claim 18 , further comprising generating, by the package controller, the fourth communication responsive to receiving the third communication, and storing the fourth communication in a buffer for transmission to the external controller.

23. The method of claim 18 , further comprising configuring, by the external controller, the rate of the encoded clock signal to minimi

Assignees

• Kioxia Corp

Inventors

• Kerr Benjamin
• Rose Philip
• Reed Robert

Classifications

• G06F13/1689 Primary

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• G06F1/3243

  Power saving in microcontroller unit · CPC title

• G06F13/4291

  using a clocked protocol · CPC title

• H04L1/004

  by using forward error control (H04L1/0618 takes precedence; coding, decoding or code conversion, for error detection or correction H03M13/00) · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title