Memory devices and methods for operating the same

Patent metadata

Field	Value
Publication number	US-11907044-B2
Application number	US-202117473905-A
Country	US
Kind code	B2
Filing date	Sep 13, 2021
Priority date	Sep 22, 2020
Publication date	Feb 20, 2024
Grant date	Feb 20, 2024

Abstract

A memory device comprises a plurality of memory cells and a plurality of evaluation elements, wherein each evaluation element of the plurality of evaluation elements is connectable with a memory cell of the memory device. The memory device further comprises an interconnection unit configured for connecting the plurality of memory cells to a first assignment of evaluation elements in a first state and for connecting the same plurality of memory cells to a second assignment of the evaluation elements in a second state. The memory device comprises an evaluation unit configured for controlling the interconnection unit to transition from the first state to the second state. The evaluation unit is configured for evaluating the plurality of memory cells in the first state to obtain a first evaluation result, and for evaluating the plurality of memory cells in the second state to obtain a second evaluation result.

First claim

The invention claimed is:

1. A memory device comprising:
a plurality of memory cells;
a plurality of evaluation elements, wherein each evaluation element of the plurality of evaluation elements is connectable with a memory cell of the memory device and is configured to evaluate a physical parameter, of the memory cell, comprising at least one of a voltage at the memory cell, a potential at the memory cell, a current through the memory cell or an electrical resistance of the memory cell;
an interconnection unit configured for:
at a first time, connecting the plurality of memory cells to a first assignment of evaluation elements in a first state; and
at a second time, connecting the plurality of memory cells to at least a second assignment of the evaluation elements in a second state, wherein in the second state, at least one memory cell of the plurality of memory cells is connected to a different evaluation element to which the at least one memory cell is not connected in the first state; and

an evaluation unit configured for:
controlling the interconnection unit to transition from (i) the first state in which the at least one memory cell is not connected to the different evaluation element to (ii) the second state in which the at least one memory cell is connected to the different evaluation element;
evaluating the plurality of memory cells in the first state, using the evaluation elements connected to the plurality of memory cells in accordance with the first assignment, to obtain a first evaluation result based on one or more first evaluations of one or more physical parameters of the plurality of memory cells; and
evaluating the plurality of memory cells in the second state, using the evaluation elements connected to the plurality of memory cells in accordance with the second assignment, to obtain a second evaluation result based on one or more second evaluations of one or more physical parameters of the plurality of memory cells.

2. The memory device of claim 1 , wherein in the first state and in the second state, each memory cell of the plurality of memory cells is connected to an evaluation element.

3. The memory device of claim 1 , wherein:
the first evaluation result represents a first bit sequence;
the second evaluation result represents a second bit sequence; and
the evaluation unit is configured for providing the first bit sequence and the second bit sequence with a same order of bits.

4. The memory device of claim 3 , wherein:
the interconnection unit comprises a re-ordering logic to implement the first assignment and the second assignment; and
the evaluation unit comprises an inverse re-ordering logic that is inverse to the re-ordering logic, wherein the inverse re-ordering logic is configured for changing an assignment of an evaluation element to a bit position from the first state to the second state inversely to the re-ordering logic to keep a bit position of a value read from a memory cell in the first bit sequence and in the second bit sequence unchanged.

5. The memory device of claim 1 , wherein the evaluation unit is configured for:
determining that a first number of bit errors in the first evaluation result exceeds a number of errors being correctable with an error correcting code being used for storing information in the plurality of memory cells;
determining that a second number of bit errors in the second evaluation result is at most the number of errors being correctable with the error correcting code; and
using the second evaluation result as a result of a read-out operation of the memory device.

6. The memory device of claim 1 , wherein the memory device is configured for determining a result of a read-out operation of the plurality of memory cells using an error detection code.

7. The memory device of claim 1 , wherein the evaluation unit is configured for:
determining that a first number of bit errors in the first evaluation result exceeds a predefined threshold; and
controlling the interconnection unit to transition to the second state based on the first number of bit errors.

8. The memory device of claim 1 , wherein the evaluation unit is configured for at least one of:
obtaining at least a third evaluation result of the plurality of memory cells using a third assignment of evaluation elements to the plurality of memory cells in a third state; or
determining a combined evaluation result as a decision by:
majority common for the plurality of memory cells; or
group-wise for groups of memory cells, wherein each group of memory cells of the groups of memory cells have at least one memory cell.

9. The memory device of claim 1 , wherein the evaluation unit is configured for repeating a read-out operation using different assignments of evaluation elements to memory cells until:
a correct or correctable read-out result is obtained; or
a termination criterion occurs.

10. The memory device of claim 1 , wherein the evaluation unit is configured for storing error information indicating that a pair of a memory cell and an evaluation element is error-prone in a memory accessible for the memory device.

11. The memory device of claim 1 , wherein the evaluation unit is configured for:
reading, from a memory, error information indicating that a pair of a memory cell of the plurality of memory cells and an evaluation element is error-prone; and
at least one of:
obtaining the second evaluation result based on the first evaluation result being based on the pair; or
avoiding the pair when evaluating the plurality of memory cells.

12. The memory device of claim 1 , wherein at least one evaluation element of the plurality of evaluation elements comprises a sense amplifier.

13. The memory device of claim 1 , wherein the plurality of memory cells is at least one of:
implemented to provide for one bit of information per memory cell;
implemented as multi-level storage; or
implemented as multi-cell storage.

14. The memory device of claim 1 , wherein the evaluation unit is configured for:
determining a deviation between at least an evaluation result of a first evaluation element in a first evaluation and an evaluation result of a second evaluation element in a second evaluation, wherein the first evaluation element and the second evaluation element are used for a same memory cell;
determining a deviation information indicating the deviation between evaluation results of the same memory cell; and
storing the deviation information in a memory of the memory device.

15. The memory device of claim 1 , wherein the memory device is configured for:
reading a deviation information from a memory, wherein the deviation information indicates a deviation between behaviors of evaluation elements; and
correcting the first evaluation result or the second evaluation result using the deviation information.

16. A memory device comprising:
a plurality of memory cells;
a plurality of evaluation elements, wherein each evaluation element of the plurality of evaluation elements is connectable with a memory cell of the memory device and is configured to evaluate a physical parameter, of the memory cell, comprising at least one of a voltage at the memory cell, a potential at the memory cell, a current through the memory cell or an electrical resistance of the memory cell;
an interconnection unit configured for:
at a first time, connecting the plurality of memory cells to a first assignment of evaluation elements in a first state; and
at a second time, connecting the plurality of memory cells to a second assignment of the evaluation elements in a second sta

Assignees

• Infineon Technologies Ag

Inventors

• Otterstedt Jan
• Allers Wolf

Classifications

• G06F11/004 Primary

  Error avoidance (G06F11/07 and subgroups take precedence) · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0634

  by changing the state or mode of one or more devices · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0673

  Single storage device · CPC title