Display substrate including a retaining wall in a frame area and display device having the same

US11903253B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11903253-B2
Application numberUS-202117459319-A
CountryUS
Kind codeB2
Filing dateAug 27, 2021
Priority dateJan 28, 2021
Publication dateFeb 13, 2024
Grant dateFeb 13, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display substrate and a display device are disclosed. The display substrate includes a display area and a frame area, and the display substrate includes a substrate, a plurality of sub-pixels on a side of the substrate, the plurality of sub-pixels are configured to emit light in the display area, an encapsulation layer on a side of the plurality of sub-pixels away from the substrate, and a retaining wall located in the frame area, the retaining wall is located between the encapsulation layer and the substrate and includes a first sub-retaining wall, a second sub-retaining wall, and a transition area between the first sub-retaining wall and the second sub-retaining wall, the retaining wall includes at least one layer provided in the same layer, the at least one layer provided in the same layer continuously extends across the first sub-retaining wall, the second sub-retaining wall and the transition area.

First claim

Opening claim text (preview).

The invention claimed is: 1. A display substrate, the display substrate comprising a display area and a frame area, the display substrate comprising: a substrate; a plurality of sub-pixels on a side of the substrate, the plurality of sub-pixels configured to emit light in the display area; an encapsulation layer on a side of the plurality of sub-pixels away from the substrate; and a retaining wall in the frame area, wherein the retaining wall is between the encapsulation layer and the substrate and comprises a first sub-retaining wall, a second sub-retaining wall, and a transition area between the first sub-retaining wall and the second sub-retaining wall, wherein the second sub-retaining wall is on a side of the first sub-retaining wall away from the display area, a vertical distance between an end of the second sub-retaining wall away from the substrate and the substrate is greater than the vertical distance between an end of the first sub-retaining wall away from the substrate and the substrate, the vertical distance between the end of the first sub-retaining wall away from the substrate and the substrate is greater than a vertical distance between and end of the transition area away from the substrate and the substrate; and wherein, the retaining wall comprises at least one layer provided in a same layer, the at least one layer provided in the same layer continuously extends across the first sub-retaining wall, the second sub-retaining wall and the transition area. 2. The display substrate according to claim 1 , wherein the display area comprises a first display area and a second display area, and the plurality of sub-pixels comprise a plurality of first sub-pixels and a plurality of second sub-pixels, wherein the plurality of first sub-pixels are in the first display area, and each first sub-pixel of the plurality of first sub-pixels comprises a first pixel drive circuit and a first light-emitting device electrically connected to the first pixel drive circuit; each second sub-pixel of the plurality of second sub-pixels comprises a second pixel drive circuit and a second light-emitting device electrically connected to the second pixel drive circuit, the second light-emitting device is in the second display area, the plurality of second sub-pixels comprise a plurality of second pixel drive circuits, at least one second pixel drive circuit of the plurality of second pixel drive circuits is not in the second display area; and the first sub-retaining wall is on a side of the at least one second pixel drive circuit away from the display area. 3. The display substrate according to claim 2 , wherein the display substrate comprises a first flat layer, wherein the at least one layer provided in the same layer comprises a first layer provided in the same layer, and wherein, the first layer provided in the same layer is provided in the same layer as the first flat layer. 4. The display substrate according to claim 3 , wherein the display substrate further comprises a second flat layer, a third flat layer, and a fourth flat layer sequentially arranged on the first flat layer, the at least one layer provided in the same layer also comprises a second layer provided in the same layer, a third layer provided in the same layer, and a fourth layer provided in the same layer sequentially arranged on the first layer provided in the same layer, and wherein, the second layer provided in the same layer is provided in the same layer as the second flat layer, the third layer provided in the same layer is provided in the same layer as the third flat layer, and the fourth layer provided in the same layer is provided in the same layer as the fourth flat layer. 5. The display substrate according to claim 4 , wherein the display substrate further comprises a fifth flat layer on the fourth flat layer, the second sub-retaining wall further comprises a fifth layer on the fourth layer provided in the same layer, and wherein, the fifth layer comprised in the second sub-retaining wall is provided in the same layer as the fifth flat layer, and an orthographic projection of the fifth layer comprised in the second sub-retaining wall on the substrate does not overlap with an orthographic projection of the transition area and the first sub-retaining wall on the substrate. 6. The display substrate according to claim 5 , wherein the display substrate further comprises a pixel defining layer on the fifth flat layer, and the second sub-retaining wall further comprises a sixth layer on the fifth layer, the first sub-retaining wall further comprises a fifth layer on the fourth layer provided in the same layer, and wherein, the sixth layer comprised in the second sub-retaining wall, the fifth layer comprised in the first sub-retaining wall, and the pixel defining layer are provided in the same layer, and an orthographic projection of the sixth layer comprised in the second sub-retaining wall on the substrate and the orthographic projection of the fifth layer comprised in the first sub-retaining wall on the substrate do not overlap with the orthographic projection of the transition area on the substrate. 7. The display substrate according to claim 6 , further comprising: at least one conduction layer, wherein the second pixel drive circuit in the frame area is electrically connected to a corresponding second light emitting device through the at least one conduction layer, and wherein the display substrate further comprises a flat layer between the at least one conduction layer and the second pixel drive circuit, and a flat layer between the at least one conduction layer and the second light emitting device. 8. The display substrate according to claim 7 , wherein the at least one conduction layer comprises a plurality of conduction layers, and wherein the display substrate further comprises a flat layer between two adjacent conduction layers among the plurality of conduction layers. 9. The display substrate according to claim 8 , wherein the plurality of conduction layers comprise a first conduction layer, a second conduction layer, and a third conduction layer, and the display substrate comprises the first flat layer, the second flat layer, the third flat layer, the fourth flat layer and the fifth flat layer sequentially arranged on the substrate, wherein the second pixel drive circuit is between the substrate and the first flat layer, wherein the first conduction layer is between the second flat layer and the third flat layer, wherein the second conduction layer is between the third flat layer and the fourth flat layer, wherein the third conduction layer is between the fourth flat layer and the fifth flat layer, and wherein the second light emitting device is on a side of the fifth flat layer away from the substrate. 10. The display substrate according to claim 7 , wherein the at least one conduction layer is light-transmissive. 11. The display substrate according to claim 9 , further comprising: a barrier layer, wherein a first end of the barrier layer extends into the first sub-retaining wall, and a second end of the barrier layer extends between the two flat layers comprised in the display substrate. 12. The display substrate according to claim 11 , wherein the first end of the barrier layer is between the second layer provided in the same layer and the third layer provided in the same layer, and the second end of the barrier layer is between the second flat layer and the third flat layer. 13. The display substrate according to claim 11 , wherein the first end of the barrier layer is between the third layer provided in the same layer and the fourth layer pr

Assignees

Inventors

Classifications

  • the pixel elements being TFTs · CPC title

  • G06F3/0446Primary

    using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes · CPC title

  • integrated with passive devices, e.g. auxiliary capacitors · CPC title

  • wherein the TFTs are in active matrices · CPC title

  • H10D86/441Primary

    Interconnections, e.g. scanning lines · CPC title

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What does patent US11903253B2 cover?
A display substrate and a display device are disclosed. The display substrate includes a display area and a frame area, and the display substrate includes a substrate, a plurality of sub-pixels on a side of the substrate, the plurality of sub-pixels are configured to emit light in the display area, an encapsulation layer on a side of the plurality of sub-pixels away from the substrate, and a re…
Who is the assignee on this patent?
Mianyang Boe Optoelectronics Tech Co Ltd, Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10K59/1213. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 13 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).