Schmitt trigger with current assistance circuit

Patent metadata

Field	Value
Publication number	US-11901900-B2
Application number	US-202217843780-A
Country	US
Kind code	B2
Filing date	Jun 17, 2022
Priority date	Jun 23, 2021
Publication date	Feb 13, 2024
Grant date	Feb 13, 2024

Abstract

An integrated circuit includes an input pad and a Schmitt trigger coupled to the input pad. The Schmitt trigger includes a main PMOS branch that charges an intermediate node of the Schmitt trigger responsive to voltage transitions at the input node. The Schmitt trigger includes a charging assistance circuit that helps to rapidly charge the intermediate node of the Schmitt trigger. The charging assistance circuit includes a parallel PMOS branch in parallel with the main PMOS branch.

First claim

The invention claimed is:

1. An integrated circuit, including:
an input pad; and
a Schmitt trigger including:
an input coupled to the input pad;
a first main transistor branch coupled between a high supply voltage and an intermediate node;
a charging assistance circuit including:
a parallel transistor branch of a first conductivity type coupled between the high supply voltage and the intermediate node;
pass transistor coupled between the input pad and the parallel transistor branch;
a switching storage element coupled to a gate terminal of the pass transistor; and
a control and reset circuit coupled to the switching storage element, the pass transistor, and the parallel transistor branch; and

a second main transistor branch coupled between the intermediate node and ground.

2. The integrated circuit of claim 1 , wherein the Schmitt trigger includes a first inverter having an input coupled to the intermediate node and an output corresponding to an output of the Schmitt trigger.

3. The integrated circuit of claim 1 , wherein the first main transistor branch and the second main transistor branch are a second inverter, wherein the input of the second inverter is the input of the Schmitt trigger, wherein the output of the second inverter is the intermediate node.

4. The integrated circuit of claim 1 , wherein the first main transistor branch supplies a charging current that charges the intermediate node from ground to the high supply voltage responsive to a transition of the input pad from a high input voltage to a low input voltage.

5. The integrated circuit of claim 4 , wherein the parallel transistor branch supplies a supplemental charging current that helps charge the intermediate node from ground to the high supply voltage responsive to the transition of the input pad from a high input voltage to a low input voltage.

6. The integrated circuit of claim 1 , wherein the first main transistor branch is a PMOS transistor branch and the parallel transistor branch is a parallel PMOS transistor branch.

7. The integrated circuit of claim 6 , wherein the main transistor branch includes a first PMOS transistor and a second PMOS transistor coupled together in series.

8. The integrated circuit of claim 7 , wherein the parallel PMOS transistor branch includes a third PMOS transistor and a fourth PMOS transistor coupled together in series.

9. A method, comprising:
supplying an input voltage from an input pad of an integrated circuit to a Schmitt trigger of the integrated circuit;
supplying a charging current from a main transistor branch of the Schmitt trigger to an intermediate node of the Schmitt trigger responsive to a transition of the input voltage from a high input value to a low input value; and
supplying a supplemental charging current from a parallel transistor branch of the Schmitt trigger to the intermediate node responsive to the transition of the input voltage from a high input value to a low input value, wherein a pass transistor is coupled between the input pad and the parallel transistor branch, a switching storage element is coupled to a gate terminal of the pass transistor, and a control and reset circuit is coupled to the switching storage element, the pass transistor, and the parallel transistor branch.

10. The method of claim 9 , wherein the main transistor branch is a PMOS transistor branch, wherein the parallel transistor branch is a parallel PMOS transistor branch.

11. The method of claim 10 , further comprising charging the intermediate node from ground to a high supply voltage by supplying the charging current and the supplemental charging current.

12. The method of claim 11 , wherein the supplemental charging current is greater than the charging current when charging the intermediate node to the high supply voltage.

13. The method of claim 12 , wherein the supplemental charging current is less than the charging current when the input voltage is at the high input value.

14. The method of claim 13 , wherein the supplemental charging current is substantially zero when the input voltage is at the high input value.

15. The method of claim 14 , further comprising turning on a PMOS transistor of the parallel PMOS transistor branch responsive to the transition.

16. The method of claim 10 , further comprising generating an output of the Schmitt trigger by inverting a voltage of the intermediate node.

17. An integrated circuit, comprising:
an input pad;
a Schmitt trigger coupled to the input pad and including:
a first inverter having:
a first main transistor branch including a first transistor of a first conductivity type; and
a second main transistor branch including a second transistor of a second conductivity type opposite of the first conductivity type coupled to the first transistor at an intermediate node of the Schmitt trigger;

a second inverter having:
an input coupled to the intermediate node; and
an output corresponding to an output of the Schmitt trigger; and

a charging assistance circuit coupled to the intermediate node and including:
a parallel transistor branch of the first conductivity type coupled between a supply voltage and the intermediate node;
a pass transistor coupled between the input pad and the parallel transistor branch;
a switching storage element coupled to a gate terminal of the pass transistor; and
a control and reset circuit coupled to the switching storage element, the pass transistor, and the parallel transistor branch.

18. The integrated circuit of claim 17 , wherein the charging assistance circuit includes a third transistor of the first conductivity type coupled to the intermediate node in parallel with the first transistor.

19. The integrated circuit of claim 18 , wherein the first transistor supplies a charging current to the intermediate node, wherein the third transistor supplies a supplemental charging current to the intermediate node.

20. The integrated circuit of claim 17 , wherein the first transistor is a PMOS transistor and the second transistor is an NMOS transistor.

Assignees

• St Microelectronics Int Nv

Inventors

• Kumar Kailash
• Kumar Manoj

Classifications

• H03K3/012 Primary

  Modifications of generator to improve response time or to decrease power consumption · CPC title

• H03K3/2893

  Bistables with hysteresis, e.g. Schmitt trigger · CPC title

• H03K3/3565 Primary

  Bistables with hysteresis, e.g. Schmitt trigger · CPC title