Array substrate and method for manufacturing the same, and display apparatus

Patent metadata

Field	Value
Publication number	US-11901375-B2
Application number	US-202117765304-A
Country	US
Kind code	B2
Filing date	Apr 13, 2021
Priority date	May 29, 2020
Publication date	Feb 13, 2024
Grant date	Feb 13, 2024

Abstract

An array substrate has a display area and a bonding area located on a side of the display area. The array substrate includes a base, a plurality of first transistors, a plurality of conductive pins and a plurality of conductive electrodes. The plurality of first transistors are disposed on a side of the base and located in the display area; a first transistor includes a first gate, a first source and a first drain. The plurality of conductive pins are disposed on the side of the base and located in the bonding area, and are disposed in a same layer as the first gate. The plurality of conductive electrodes are each disposed on a respective one of surfaces of the plurality of conductive pins away from the base.

First claim

What is claimed is:

1. An array substrate having a display area and a bonding area located on a side of the display area; the array substrate comprising:
a base;
a plurality of first transistors disposed on a side of the base and located in the display area, and a first transistor including a first gate, a first source, and a first drain;
a plurality of conductive pins disposed on the side of the base and located in the bonding area, and the plurality of conductive pins being disposed in a same layer as the first gate; and
a plurality of conductive electrodes each disposed on a respective one of surfaces of the plurality of conductive pins away from the base.

2. The array substrate according to claim 1 , further comprising: a plurality of touch signal lines disposed on the side of the base and extending in a first direction, wherein
the plurality of touch signal lines are disposed in a same layer as the first source and the first drain; and
at least one touch signal line is electrically connected to one conductive pin.

3. The array substrate according to claim 2 , further comprising: a plurality of touch electrodes disposed on a side of the plurality of touch signal lines away from the base, wherein
each touch electrode is electrically connected to at least one touch signal line.

4. The array substrate according to claim 3 , further comprising:
a planarization layer disposed between the plurality of first transistors and the plurality of touch electrodes, wherein
the planarization layer has a plurality of first via holes, and each touch signal line is electrically connected to a touch electrode through at least one first via hole; and
an orthogonal projection of the planarization layer on the base does not overlap with orthogonal projections of the plurality of conductive pins on the base.

5. The array substrate according to claim 3 , further comprising: a plurality of pixel electrodes disposed on a side of the plurality of touch electrodes away from or proximate to the base, wherein
one of a first source and a first drain of each first transistor is electrically connected to a pixel electrode; and
the plurality of conductive electrodes are disposed in a same layer as the plurality of touch electrodes or the plurality of pixel electrodes.

6. The array substrate according to claim 5 , further comprising: a plurality of data lines disposed in a same layer as the plurality of touch signal lines and extending in the first direction, wherein
another of the first source and the first drain of each first transistor is electrically connected to a data line; and
at least one data line is electrically connected to one conductive pin.

7. The array substrate according to claim 2 , further comprising: a plurality of connection portions, wherein
the conductive pin is electrically connected to the at least one touch signal line through a connection portion.

8. The array substrate according to claim 7 , further comprising: a plurality of touch electrodes, wherein
the plurality of connection portions are disposed in a same layer as the plurality of touch electrodes, and each of the plurality of connection portions and a respective one of the plurality of conductive electrodes are of an integrated structure; and
an end of the connection portion is electrically connected to the at least one touch signal line.

9. The array substrate according to claim 7 , wherein the connection portion includes a multiplexer; and
an input end of the multiplexer is electrically connected to the conductive pin, and output ends of the multiplexer is electrically connected to at least two touch signal lines.

10. The array substrate according to claim 9 , wherein the multiplexer includes at least two second transistors, and a second transistor includes a second source and a second drain; and
one of the second source and the second drain is, as the input end, electrically connected to the conductive pin, and another of the second source and the second drain is, as the output end, electrically connected to one of the at least two touch signal lines.

11. The array substrate according to claim 2 , further comprising: an insulating layer disposed between a layer where the first source and the first drain are located and the first gate, wherein
the insulating layer is provided with a plurality of second via holes therein, and each touch signal line is electrically connected to a conductive pin through at least one second via hole.

12. The array substrate according to claim 1 , wherein orthogonal projections of the plurality of conductive pins on the base are each located within an orthogonal projection of a respective one of the plurality of conductive electrodes on the base.

13. The array substrate according to claim 1 , further comprising: an insulating layer disposed between a layer where the first source and the first drain are located and the first gate, wherein
an orthogonal projection of the insulating layer on the base does not overlap with orthogonal projections of the plurality of conductive pins on the base.

14. A method for manufacturing an array substrate, comprising:
providing a base; the base having a display area and a bonding area located on a side of the display area;
forming a plurality of first transistors and a plurality of conductive pins on a side of the base; the plurality of first transistors being located in the display area, and a first transistor including a first gate, a first source and a first drain; and the plurality of conductive pins being located in the bonding area and disposed in a same layer as the first gate; and
forming a plurality of conductive electrodes each on a respective one of surfaces of the plurality of conductive pins away from the base.

15. The method for manufacturing the array substrate according to claim 14 , wherein a step of forming the plurality of first transistors includes:
forming a source-drain conductive film on the side of the base; and
patterning the source-drain conductive film to remove a portion of the source-drain conductive film located in the bonding area, and form a plurality of touch signal lines, and first sources and first drains of the plurality of first transistors in the display area.

16. The method for manufacturing the array substrate according to claim 15 , wherein before forming the plurality of conductive electrodes, the method for manufacturing the array substrate further comprises:
forming a planarization film on a side of the plurality of touch signal lines, the plurality of first transistors, and the plurality of conductive pins away from the base; and
patterning the planarization film to form first via holes, exposing the plurality of touch signal lines, in the planarization film, and remove a portion of the planarization film located in the bonding area, so as to obtain a planarization layer; an orthogonal projection of the planarization layer on the base not overlapping with orthogonal projections of the plurality of conductive pins on the base.

17. A display apparatus, comprising:
the array substrate according to claim 1 ;
an opposite substrate disposed opposite to the array substrate; and
a liquid crystal layer disposed between the array substrate and the opposite substrate.

18. The display apparatus according to claim 17 , further comprising: a chip on film bonded to the plurality of conductive electrodes in the array substrate.

19. The array substrate according to claim 7 , further comprising: a plurality of pixel electrodes, wherein
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Assignees

• Ordos Yuansheng Optoelectronics Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Ju Yongbo
• Cui Pengfei
• Sun Jian
• Wang Deshuai
• Shen Xiangkai
• Gao Jianbin
• Wang Jiannan
• Wang Guangshuai

Classifications

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/9223

  with redistribution layers [RDL] · CPC title

• H10W72/01953

  by etching · CPC title

• H10W72/01951

  Changing the shapes of bond pads · CPC title

• H10W72/01938

  in gaseous form, e.g. by CVD or PVD · CPC title