Semiconductor packages with integrated shielding

Patent metadata

Field	Value
Publication number	US-11901308-B2
Application number	US-202117382283-A
Country	US
Kind code	B2
Filing date	Jul 21, 2021
Priority date	Jul 21, 2020
Publication date	Feb 13, 2024
Grant date	Feb 13, 2024

Abstract

The present disclosure is directed to improving EMI shielding to provide more reliable semiconductor packages. The semiconductor package may be, for example, a lead frame including one or multiple dies attached thereto. The semiconductor package may include only wire bonds or a combination of clip bonds and wire bonds. An integrated shielding structure may be disposed in between the package substrate and the encapsulant to shield internal and/or external EMI. For example, a top surface of the integrated shield structure is exposed.

First claim

The invention claimed is:

1. A device comprising:
a package substrate having a die attach pad (DAP) and package pads;
a die disposed on the DAP, the die is electrically coupled to the package pads;
a primary electromagnetic interference (EMI) shield structure, the primary EMI shield structure comprises
a primary EMI planar member covering the die,
a first primary EMI leg member contiguous to a first side of the primary EMI planar member and extending downwards to the package substrate, the primary EMI shield structure forms a cavity over the die in which a cavity height of the cavity is defined by the first primary EMI leg member, wherein adjacent opposing sides of the first side of the primary EMI planar member do not include leg members extending downwards to the package substrate, leaving the die exposed on the adjacent opposing sides of the primary EMI planar member, and
wherein the primary EMI shield structure is electrically coupled to ground; and

an encapsulant, the encapsulant covers the first primary EMI leg member and the package substrate.

2. The device of claim 1 further comprises a thermal interface layer (TIL) disposed on a top die surface of the die and contacts a bottom surface of the primary EMI planar member, the TIL enables the primary EMI shield structure to further serve as a heat dissipator.

3. The device of claim 1 wherein the primary EMI shield structure comprises a second primary EMI leg member contiguous to a second side of the planar member which is an opposing side of the first side, the second primary EMI leg member extends downwards to the package substrate.

4. The device of claim 3 further comprises a thermal interface layer (TIL) disposed on a top die surface of the die and contacts a bottom surface of the primary EMI planar member, the TIL enables the primary EMI shield structure to further serve as a heat dissipator.

5. The device of claim 1 further includes a secondary EMI shield structure, wherein the secondary EMI shield structure comprises:
a secondary EMI planar member which contacts a top surface of the primary EMI planar member; and
the secondary EMI shield structure contacts a top encapsulant surface of the encapsulant which is coplanar with the top surface of the primary EMI planar member, wherein the top surface of the secondary EMI shield structure, the secondary EMI shield structure serves as an external EMI shield structure of the device, wherein the secondary EMI shield structure is coupled to ground by contacting the primary EMI shield structure.

6. The device of claim 5 further comprises a thermal interface layer (TIL) disposed on a top die surface of the die and contacts a bottom surface of the primary EMI planar member, the TIL enables the primary and secondary EMI shield structures to further serve as a heat dissipator.

7. The device of claim 5 wherein the secondary EMI shield structure comprises:
the secondary EMI planar members; and
secondary EMI side members, wherein the secondary EMI planar member and side members encase the primary EMI shield structure and encapsulant, the secondary EMI shield structure serves as an external EMI shield structure of the device, wherein the secondary EMI shield structure is coupled to ground by contacting the primary EMI shield structure.

8. The device of claim 7 further comprises a thermal interface layer (TIL) disposed on a top die surface of the die and contacts a bottom surface of the primary EMI planar member, the TIL enables the primary and secondary EMI shield structures to further serve as a heat dissipator 2 .

9. The device of claim 7 wherein the primary EMI shield structure comprises a second primary EMI leg member contiguous to a second side of the planar member which is an opposing side of the first side, the second primary EMI leg member extends downwards to the package substrate.

10. The device of claim 9 wherein:
side surfaces of the encapsulation layer comprise a step profile, wherein
a lower portion of the step profile of the encapsulation layer is aligned with side package substrate surfaces of the package substrate, and
an upper portion of the step profile of the encapsulation layer is recessed from the lower portion; and

side secondary EMI members are disposed on the upper portion of step profile of the encapsulation layer and isolated from the package substrate by the lower portion of the step profile of the encapsulation layer to prevent the package pads from being shorted to ground.

11. The device of claim 7 wherein:
side surfaces of the encapsulation layer comprise a step profile, wherein
a lower portion of the step profile of the encapsulation layer is aligned with side package substrate surfaces of the package substrate, and
an upper portion of the step profile of the encapsulation layer is recessed from the lower portion; and

side secondary EMI members are disposed on the upper portion of step profile of the encapsulation layer and isolated from the package substrate by the lower portion of the step profile of the encapsulation layer to prevent the package pads from being shorted to ground.

12. The device of claim 1 further comprises:
a secondary EMI shield structure, wherein the secondary EMI shield structure includes
a secondary EMI planar member which contacts a top surface of the primary EMI planar member, and
the secondary EMI shield structure contacts a top encapsulant surface of the encapsulant which is coplanar with the top surface of the primary EMI planar member, wherein the secondary EMI shield structure is coupled to ground by contacting the primary EMI shield structure;

a tertiary EMI shield structure, the tertiary EMI shield structure includes
a tertiary EMI planar member contacting a top surface of the secondary EMI planar member, and
tertiary EMI side members, wherein the tertiary EMI planar member and side members encase the primary and secondary EMI shield structures to serve as an external EMI shield structure of the device, wherein the tertiary EMI shield structure is coupled to ground by contacting the secondary EMI shield structure.

13. The device of claim 12 further comprises a thermal interface layer (TIL) disposed on a top die surface of the die and contacts a bottom surface of the primary EMI planar member, the TIL enables the primary and secondary EMI shield structures to further serve as a heat dissipator.

14. A device comprising:
a package substrate having a die attach pad (DAP) and package pads;
a die disposed on the DAP, the die is electrically coupled to the package pads;
an encapsulation layer, the encapsulation layer covers the package substrate and the die, the encapsulation layer having a top encapsulation surface disposed above a top die surface;
a primary electromagnetic interference (EMI) shield structure, the primary EMI shield structure comprises a primary EMI planar member, the primary EMI planar member is disposed on the top encapsulation surface; and
a secondary EMI shield structure, the secondary EMI shield structure comprises
a secondary EMI planar member the secondary EMI planar member disposed on a top primary planar surface of the primary EMI planar member,
secondary EMI side members, the secondary EMI side members extend downwards from second planar member side surfaces of the secondary EMI planar member towards the package substrate,
the secondary EMI shield structure encases the primary EMI shield structure, the die and encapsulation layer, the secondary EMI shield structure serves as an external EMI shield structure of the device, and
wherein the secondary EMI shield structure is coupled to ground.

Assignees

• Utac Headquarters Pte Ltd

Inventors

• Sirinorakul Saravuth
• Shim Il Kwon
• Lock Kok Chuen
• Robles Roel Adeva
• Dumsong Eakkasit

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W74/01

  Manufacture or treatment · CPC title

• H10W70/411

  Chip-supporting parts, e.g. die pads · CPC title

• H10W40/10

  Arrangements for heating · CPC title