Magnetoresistive asymmetry compensation

Patent metadata

Field	Value
Publication number	US-11900970-B2
Application number	US-202117162218-A
Country	US
Kind code	B2
Filing date	Jan 29, 2021
Priority date	Jan 29, 2021
Publication date	Feb 13, 2024
Grant date	Feb 13, 2024

Abstract

Systems and methods are disclosed for magnetoresistive asymmetry compensation using a hybrid analog and digital compensation scheme. In certain embodiments, a method may comprise receiving an analog signal at a continuous-time front end (CTFE) circuit, and performing, via the CTFE circuit, first magnetoresistive asymmetry (MRA) compensation on the analog signal to adjust the dynamic range of the analog signal based on an input range of an analog-to-digital converter (ADC). The method may further comprise converting the analog signal to a digital sample sequence via the ADC, and performing, via a digital MRA compensation circuit, second MRA compensation to correct residual MRA in the digital sample sequence. Offset compensation may also be performed in both the analog and digital domains.

First claim

What is claimed is:

1. An apparatus comprising: a continuous-time front end (CTFE) configured to: receive an analog signal; perform first magnetoresistive asymmetry (MRA) compensation on the analog signal to adjust a dynamic range of the analog signal based on an input range of an analog-to-digital converter (ADC); the ADC, configured to convert the analog signal to a digital sample sequence; and a digital MRA compensation circuit configured to perform second MRA compensation to correct residual MRA in the digital sample sequence; a magnetic disc storage medium; a read element configured to: detect a magnetic field from the magnetic disc storage medium; generate the analog signal based on the magnetic field; provide the analog signal to the CTFE; and a read/write channel including the CTFE, the ADC, and the digital MRA compensation circuit.

2. The apparatus of claim 1 further comprising:
a first MRA estimation circuit configured to:
receive the digital sample sequence from the ADC;
determine a first MRA compensation value based on the digital sample sequence; and
provide the first MRA compensation value to the CTFE for use in the first MRA compensation.

3. The apparatus of claim 2 further comprising:
a second MRA estimation circuit configured to:
receive an MRA-compensated digital sample sequence from the digital MRA compensation circuit;
determine a second MRA compensation value based on the MRA-compensated digital sample sequence; and
provide the second MRA compensation value to the digital MRA compensation circuit for use in the second MRA compensation.

4. The apparatus of claim 3 further comprising:
a digital backend circuit configured to:
receive the MRA-compensated digital sample sequence from the digital MRA compensation circuit; and
process the MRA-compensated digital sample sequence to determine a sequence of user bits corresponding to the analog signal.

5. The apparatus of claim 4 further comprising:
the CTFE configured to apply a fixed value for the first MRA compensation, the fixed value selected to cancel a majority of MRA influence prior to providing the analog signal to the ADC; and
the digital MRA compensation circuit configured to correct a residual MRA influence remaining after the first MRA compensation.

6. The apparatus of claim 5 further comprising:
the fixed value is selected based on an observed magnitude of the residual MRA influence in the digital sample sequence applied to the digital MRA compensation circuit, to minimize the residual MRA influence.

7. The apparatus of claim 5 further comprising:
the fixed value is selected based on a first counter which counts a number of samples above a positive threshold and a second counter which counts a number of samples below a negative threshold; and
the CTFE is configured to recalibrate the fixed value when a difference between the first counter and the second counter exceeds a threshold value.

8. The apparatus of claim 5 further comprising:
the first MRA estimation circuit is a first MRA and offset estimation circuit, and further configured to:
determine a first DC offset value based on the digital sample sequence;
provide the first DC offset value to the CTFE;

the CTFE further configured to perform a first DC offset compensation on the analog signal based on the first DC offset value;
the first MRA and offset estimation circuit is further configured to:
determine a second DC offset value based on the MRA-compensated digital sample sequence;
provide the second DC offset value to the digital MRA compensation circuit; and

the digital MRA compensation circuit is a digital MRA and offset compensation circuit, and further configured to perform a second DC offset compensation on the digital sample sequence based on the second DC offset value.

9. The apparatus of claim 8 further comprising:
the digital MRA and offset compensation circuit configured to perform the second MRA compensation and the second DC offset compensation, further including:
add the DC offset value to the digital sample sequence via a first adder to produce an offset-compensated signal;
apply the offset-compensated signal to a squaring operation to produce a squared offset-compensated signal;
multiply the squared offset-compensated signal and the second MRA compensation value via a multiplier to produce an MRA compensated signal;
combine the offset-compensated signal and the MRA compensated signal via a second adder to produce a digitally compensated signal; and
provide the digitally compensated signal to the digital backend circuit.

10. A method comprising:
receiving an analog signal at a continuous-time front end (CTFE) circuit;
performing, via the CTFE circuit, first magnetoresistive asymmetry (MRA) compensation on the analog signal to adjust a dynamic range of the analog signal based on an input range of an analog-to-digital converter (ADC), including:
applying a fixed value for the first MRA compensation, the fixed value selected to cancel a majority of MRA influence prior to providing the analog signal to the ADC;

converting the analog signal to a digital sample sequence via the ADC; and
performing, via a digital MRA compensation circuit, second MRA compensation to correct residual MRA in the digital sample sequence, including:
correcting, via the digital MRA compensation circuit, a residual MRA influence remaining after the first MRA compensation.

11. The method of claim 10 further comprising:
receiving, at a first MRA and offset estimation circuit, the digital sample sequence from the ADC;
determining, at the first MRA and offset estimation circuit, a first MRA compensation value based on the digital sample sequence;
determining, at the first MRA and offset estimation circuit, a first DC offset value based on the digital sample sequence;
providing the first MRA compensation value and the first DC offset value to the CTFE;
performing, via the CTFE, the first MRA compensation based on the first MRA compensation value; and
performing, via the CTFE, a first DC offset compensation on the analog signal based on the first DC offset value.

12. The method of claim 11 further comprising:
the digital MRA compensation circuit is a digital MRA and offset compensation circuit;
receiving, at a second MRA and offset estimation circuit, an MRA-compensated digital sample sequence from the digital MRA and offset compensation circuit;
determining, at the second MRA and offset estimation circuit, a second MRA compensation value based on the MRA-compensated digital sample sequence;
determining, at the second MRA and offset estimation circuit, a second DC offset value based on the MRA-compensated digital sample sequence;
providing the second MRA compensation value and the second DC offset value to the digital MRA and offset compensation circuit;
performing, via the digital MRA and offset compensation circuit, the second MRA compensation based on the second MRA compensation value; and
performing, via the digital MRA and offset compensation circuit, a second DC offset compensation on the digital sample sequence based on the second DC offset value.

13. The method of claim 10 , further comprising:
receiving, via a digital backend (DBE) circuit, an MRA-compensated digital sample sequence from the digital MRA compensation circuit; and
processing, via the DBE circuit, the MRA-compensated digital sample sequence to determine a sequence of user bits corresponding to the analog signal.

14. The method of claim 10 , further comprising:
selecting the fixed value based on an observed magnitude of the residual MRA influence in the digit

Assignees

• Seagate Technology Llc

Inventors

• Bellorado Jason
• Marrow Marcus
• Wu Zheng

Classifications

• G11B5/09 Primary

  Digital recording · CPC title

• G06F13/385

  for adaptation of a particular data processing system to different peripheral devices · CPC title

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• G11B2005/0013

  of transducers, e.g. linearisation, equalisation · CPC title

• H03M1/181 Primary

  in feedback mode, i.e. by determining the range to be selected from one or more previous digital output values · CPC title