Graphics neural network processor, method, and system

Patent metadata

Field	Value
Publication number	US-11900665-B2
Application number	US-202318358067-A
Country	US
Kind code	B2
Filing date	Jul 25, 2023
Priority date	Apr 24, 2017
Publication date	Feb 13, 2024
Grant date	Feb 13, 2024

Abstract

A graphics processor can include a processing cluster array including a plurality of processing clusters coupled with the plurality of memory controllers, each processing cluster of the plurality of processing clusters including a plurality of streaming multiprocessors, the processing cluster array configured for partitioning into a plurality of partitions. The plurality of partitions include a first partition including a first plurality of streaming multiprocessors configured to perform operations for a first neural network, The operations for the first neural network are isolated to the first partition. The plurality of partitions also include a second partition including a second plurality of streaming multiprocessors configured to perform operations for a second neural network. The operations for the second neural network are isolated to the second partition and protected from operations performed for the first neural network.

First claim

What is claimed is:

1. A graphics processor comprising:
a plurality of memory controllers associated with a plurality of memory partitions;
a level-two (L2) cache including a plurality of cache partitions associated with the plurality of memory partitions;
a processing cluster array including a plurality of processing clusters coupled with the plurality of memory controllers, each processing cluster of the plurality of processing clusters including a plurality of streaming multiprocessors, the processing cluster array configured for partitioning into a plurality of partitions, the plurality of partitions including:
a first partition including a first plurality of streaming multiprocessors configured to perform operations for a first neural network, the operations for the first neural network isolated to the first partition; and
a second partition including a second plurality of streaming multiprocessors configured to perform operations for a second neural network, the operations for the second neural network are isolated to the second partition and protected from operations performed for the first neural network.

2. The graphics processor of claim 1 , comprising:
a first processing cluster including the first plurality of streaming multiprocessors; and
a second processing cluster including the second plurality of streaming multiprocessors.

3. The graphics processor of claim 1 , wherein each of the plurality of memory partitions is respectively associated with a memory controller of the plurality of memory controllers.

4. The graphics processor of claim 3 , wherein each of the plurality of memory partitions is respectively associated with a cache partition of the plurality of cache partitions.

5. The graphics processor of claim 4 , the first plurality of streaming multiprocessors associated with a first memory path that includes a first cache partition and a first memory controller.

6. The graphics processor of claim 5 , the second plurality of streaming multiprocessors associated with a second memory path that includes a second cache partition and a second memory controller, the second memory path isolated from the first memory path.

7. The graphics processor of claim 1 , comprising circuitry to authenticate access to data associated with the first neural network and the second neural network.

8. The graphics processor of claim 7 , the circuitry to facilitate authenticated access to secured data of the first neural network by the first partition.

9. The graphics processor of claim 7 , the circuitry to facilitate authenticated access to secured data of the second neural network by the second partition.

10. The graphics processor of claim 1 , wherein the processing cluster array and a memory controller of the plurality of memory controllers share a semiconductor die.

11. A method comprising:
performing operations for a first neural network, the operations for the first neural network performed on a graphics processor having a plurality of memory controllers associated with a plurality of memory partitions, a level-two (L2) cache including a plurality of cache partitions associated with the plurality of memory partitions, and a processing cluster array including a plurality of processing clusters coupled with the plurality of memory controllers, each processing cluster of the plurality of processing clusters including a plurality of streaming multiprocessors, the processing cluster array configured for partitioning into a plurality of partitions including a first partition and a second partition, wherein the first partition includes a first plurality of streaming multiprocessors and the operations for the first neural network are isolated to the first partition; and
performing operations for a second neural network via the second partition, wherein the second partition includes a second plurality of streaming multiprocessors and operations for the second neural network are isolated to the second partition.

12. The method of claim 11 , comprising facilitating authenticated access to secured data of the first neural network by the first partition via circuitry configured to authenticate access to data associated with the first neural network.

13. The method of claim 11 , comprising facilitating authenticated access to secured data of the second neural network by the second partition via circuitry configured to authenticate access to data associated with the second neural network.

14. The method of claim 11 , comprising:
performing operations for the first neural network via a first processing cluster of the plurality of processing clusters, wherein the first processing cluster includes the first plurality of streaming multiprocessors, the first plurality of streaming multiprocessors is associated with a first memory path that includes a first cache partition of the plurality of cache partitions and a first memory controller of the plurality of memory controllers; and
performing operations for the second neural network via a second processing cluster of the plurality of processing clusters, wherein the second processing cluster includes the second plurality of streaming multiprocessors, the second plurality of streaming multiprocessors is associated with a second memory path that includes a second cache partition of the plurality of cache partitions and a second memory controller of the plurality of memory controllers.

15. The method of claim 14 , wherein the first memory path is isolated from the second memory path.

16. A graphics processing system comprising:
a memory device configured for partitioning into a plurality of memory partitions;
a plurality of memory controllers associated with the plurality of memory partitions;
a level-two (L2) cache including a plurality of cache partitions associated with the plurality of memory partitions;
a processing cluster array including a plurality of processing clusters coupled with the plurality of memory controllers, each processing cluster of the plurality of processing clusters including a plurality of streaming multiprocessors, the processing cluster array configured for partitioning into a plurality of partitions, the plurality of partitions including:
a first partition including a first plurality of streaming multiprocessors configured to perform operations for a first neural network, the operations for the first neural network isolated to the first partition; and
a second partition including a second plurality of streaming multiprocessors configured to perform operations for a second neural network, the operations for the second neural network are isolated to the second partition and protected from operations performed for the first neural network.

17. The graphics processing system of claim 16 , comprising:
a first processing cluster including the first plurality of streaming multiprocessors; and
a second processing cluster including the second plurality of streaming multiprocessors.

18. The graphics processing system of claim 16 , wherein each of the plurality of memory partitions is respectively associated with a memory controller of the plurality of memory controllers.

19. The graphics processing system of claim 18 , wherein each of the plurality of memory partitions is respectively associated with a cache partition of the plurality of cache partitions.

20. The graphics processing system of claim 19 , the first plurality of streaming multiprocessors associated with a first memory path that includes a first cache partition and a first memory controller.

Assignees

• Intel Corp

Inventors

• Das Barnan
• Varerkar Mayuresh M
• Biswal Narayan
• Baran Stanley J
• Cilingir Gokcen
• Shah Nilesh V
• Sharma Archie
• Abdelhak Sherine
• Kotha Praneetha
• Pandit Neelay
• Weast John C
• Macpherson Mike B
• Kim Dukhwan
• Hurd Linda L
• Appu Abhishek R
• Koker Altug
• Ray Joydeep

Classifications

• G06F16/5862

  using texture · CPC title

• G06F16/5838

  using colour · CPC title

• G06V10/82 Primary

  using neural networks · CPC title

• G06V10/764

  using classification, e.g. of video objects · CPC title

• G06V40/103

  Static body considered as a whole, e.g. static pedestrian or occupant recognition · CPC title