Integrated circuit chip apparatus

Patent metadata

Field	Value
Publication number	US-11900241-B2
Application number	US-202217688844-A
Country	US
Kind code	B2
Filing date	Mar 7, 2022
Priority date	Dec 14, 2017
Publication date	Feb 13, 2024
Grant date	Feb 13, 2024

Abstract

Provided are an integrated circuit chip apparatus and a related product, the integrated circuit chip apparatus being used for executing a multiplication operation, a convolution operation or a training operation of a neural network. The present technical solution has the advantages of a small amount of calculation and low power consumption.

First claim

The invention claimed is:

1. An integrated circuit chip apparatus, comprising:
a main processing circuit; and
a plurality of basic processing circuits comprising data type conversion circuits configured to convert data between a floating data type and a fixed point data type,
wherein the main processing circuit is configured to transfer data and a computation instruction to the plurality of basic processing circuits,
wherein the plurality of basic processing circuits are configured to, when convert the data transferred to the basic processing circuits is in the floating point data type:
convert the data into the fixed point data type;
perform a first set of neural network computations in parallel in the fixed point data type on the data to obtain computation results in the fixed point data type;
convert the computation results in the fixed point data type into the floating point data type; and
transfer the computation results to the main processing circuit in the floating point data type.

2. The integrated circuit chip apparatus of claim 1 , wherein the main processing circuit is further configured to perform a second set of neural network computations in series on the computation results to obtain an instruction result of the data and the computation instruction.

3. The integrated circuit chip apparatus of claim 2 ,
wherein the main processing circuit is further configured to perform the second set of neural network computations on the computation results in the floating point data type to obtain the instruction result.

4. The integrated circuit chip apparatus of claim 2 , wherein the first set of neural network computations are inner product computations, and the second set of neural network computations include accumulations of the computation results to obtain accumulation results, and sorting of the accumulation results to obtain an instruction result of the data and the computation instruction.

5. The integrated circuit chip apparatus of claim 1 , wherein the plurality of basic processing circuits include k basic processing circuits connected to the main processing circuit and the other basic processing circuits connected to the k basic processing circuits,
wherein the main processing circuit is configured to transfer data and a computation instruction to the k basic processing circuits,
wherein the k basic processing circuits are configured to forward data received from the main processing circuit to the other basic processing circuits among the plurality of basic processing circuits.

6. The integrated circuit chip apparatus of claim 3 , wherein the main processing circuit is further configured to:
divide the data into a distribution data block and a broadcasting data block according to the computation instruction;
partition the distribution data block into the plurality of basic data blocks;
distribute the plurality of basic data blocks to the k basic processing circuits; and
broadcast the broadcasting data block to the k basic processing circuits.

7. The integrated circuit chip apparatus of claim 6 , wherein the plurality of basic processing circuits are further configured to:
convert the basic data blocks and the broadcasting data block from the floating point data type into the fixed point data type;
perform the first set of neural network computations in the fixed point data type on the basic data blocks and the broadcasting data block to obtain the computation results in the fixed point data type;
convert the computation results into the floating point data type; and
transfer the computation results in the floating point data type to the main processing circuit through the k basic processing circuits.

8. The integrated circuit chip apparatus of claim 6 , wherein the main processing circuit is further configured to divide the broadcasting data block into a plurality of partial broadcasting data blocks, and sequentially broadcast the plurality of partial broadcasting data blocks to the k basic processing circuits.

9. The integrated circuit chip apparatus of claim 8 , wherein the plurality of basic processing circuits are configured to:
convert the partial broadcasting data blocks and the basic data blocks from the floating point data type into the fixed point data type;
perform the first set of neural network computations in the fixed point data type to obtain partial computation results in the fixed point data type;
convert the partial computation results into the floating point data type; and
send the partial computation results in the floating point data type to the main processing circuit through the k basic processing circuits.

10. The integrated circuit chip apparatus of claim 5 , wherein the basic processing circuits are arranged in an array comprising m rows and n columns of basic processing circuits, wherein the k basic processing circuits are the m basic processing circuits in the first column or the last column of the array or the n basic processing circuits in the first row or the last row of the array.

11. The integrated circuit chip apparatus of claim 1 , wherein the plurality of basic processing circuits are configured to, when the data transferred to the basic processing circuits is in the fixed point data type:
perform a first set of neural network computations in parallel in the fixed point data type on the data to obtain the computation results in the fixed point data type; and
transfer computation results to the main processing circuit.

12. The integrated circuit chip apparatus of claim 1 , wherein
the main processing circuit includes a main register or a main on-chip caching circuit, and
each of the plurality of basic processing circuits includes a basic register or a basic on-chip caching circuit.

13. The integrated circuit chip apparatus of claim 1 , wherein the main processing circuit includes one or more of a vector computing unit circuit, an arithmetic and logic unit circuit, an accumulator circuit, a matrix transposition circuit, a direct memory access circuit, a data type conversion circuit, or a data rearrangement circuit.

14. The integrated circuit chip apparatus of claim 1 , wherein the data is one or more of a vector, a matrix, or an n-dimensional data block, wherein n is an integer greater than 2.

15. A processing system, comprising:
a neural network computing apparatus;
a general interconnection interface; and
a general-purpose processing apparatus connected to the neural network computing apparatus via the general interconnection interface,
wherein the neural network computing apparatus further comprises:
a main processing circuit; and
a plurality of basic processing circuits comprising data type conversion circuits configured to convert data between a floating data type and a fixed point data type,
wherein the main processing circuit is configured to transfer data and a computation instruction to the plurality of basic processing circuits,
wherein the plurality of basic processing circuits are configured to, when the data transferred to the basic processing circuits is in the floating point data type:
convert the data into the fixed point data type;
perform a first set of neural network computations in parallel in the fixed point data type on the data to obtain computation results in the fixed point data type;
convert the computation results in the fixed point data type into the floating point data type: and
transfer the computation results to the main processing circuit in the floating point data type.

16. The processing system of claim 15 , wherein the main processing circuit is further conf

Assignees

• Cambricon Tech Corp Ltd

Inventors

• Liu Shaoli
• Song Xinkai
• Wang Bingrui
• Zhang Yao
• Hu Shuai

Classifications

• H10W90/00

  Package configurations · CPC title

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G06N3/063 Primary

  using electronic means · CPC title

• G06F7/483

  Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)} · CPC title

• G06F7/5443

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title