Enhanced auxiliary memory mapped interface test systems and methods

Patent metadata

Field	Value
Publication number	US-11899550-B2
Application number	US-202117161417-A
Country	US
Kind code	B2
Filing date	Jan 28, 2021
Priority date	Mar 31, 2020
Publication date	Feb 13, 2024
Grant date	Feb 13, 2024

Abstract

Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, an enhanced auxiliary interface test system comprises a load board, testing electronics, controller, and memory mapped interface. The load board is configured to couple with a plurality of devices under test (DUTs). The testing electronics is configured to test the plurality of DUTs, wherein the testing electronics are coupled to the load board. The controller is configured to direct testing of the DUTs, wherein the controller is coupled to the testing electronics. The memory mapped interface is configured to implement multiple paths to access a central processing unit (CPU) on the controller and enable testing of multiple DUTs in parallel.

First claim

What is claimed is:

1. An enhanced auxiliary interface test system comprises:
a load board configured to couple with a plurality of devices under test (DUTs);
testing electronics configured to test the plurality of DUTs, wherein the testing electronics are coupled to the load board;
a controller configured to direct testing of the DUTs, wherein the controller is coupled to the testing electronics; and
a memory mapped interface configured to implement multiple paths to access a central processing unit (CPU) on the controller and enable testing of multiple DUTs in parallel, wherein the memory mapped interface is supported by modifications to a field programmable gate array (FPGA), a driver, and a user space.

2. An enhanced auxiliary interface test system of claim 1 wherein the plurality of DUTs are non-volatile memory express (NVMe) devices with a universal asynchronous receiver-transmitter (UART) interface.

3. An enhanced auxiliary interface test system of claim 2 wherein the NVMe devices have a UART interface over peripheral component interconnect express (PCIe).

4. An enhanced auxiliary interface test system of claim 1 wherein the plurality of DUTs are peripheral component interconnect express (PCIe) Non Volatile Memory Express (NVMe) solid state drives (SSDs).

5. An enhanced auxiliary interface test system of claim 1 wherein the controller provides for test systems with multi-function devices that can work in an environment with more than one of the plurality of DUTs per central processing unit (CPU).

6. An enhanced auxiliary interface test system of claim 1 wherein the memory mapped interface enables a first number of serial buses to increase to a second number of serial buses, wherein the second number of serial buses is beyond limitations of an input/output (I/O) space address of the controller, which in turn enables more devices to be connected and tested at least in part concurrently or in parallel.

7. An enhanced auxiliary interface test method comprising:
coupling a plurality of devices under test (DUTs) to a loadboard;
testing the plurality of DUTs coupled to the loadboard;
configuring multiple paths for access to a central processing unit (CPU) and testing the plurality of DUTs in parallel, wherein the configuring utilizes a flexible enhanced auxiliary interface;
modifying a field programmable gate array (FPGA), a driver, and a user space to support the flexible enhanced auxiliary interface; and
directing testing of the plurality of DUTs in accordance with the multiple paths.

8. An enhanced auxiliary interface test method of claim 7 wherein the DUTs are NVMe devices with a universal asynchronous receiver-transmitter (UART) interface.

9. An enhanced auxiliary interface test method of claim 7 wherein the directing testing of the plurality of DUTs includes directing debug operations.

10. An enhanced auxiliary interface test method of claim 7 wherein the directing testing of the plurality of DUTs included providing for test systems with multi-function devices that can work in an environment with more than one of the plurality of DUTs per the CPU.

11. An enhanced auxiliary interface test method of claim 7 wherein the configuring multiple paths for access to the CPU enables a first number of serial buses to increase to a second number of serial buses, wherein the second number of serial buses is beyond limitations of an input/output (I/O) space address of the CPU.

12. An enhanced auxiliary interface test method of claim 7 includes utilizing the configuring of the multiple paths for access to the flexible enhanced auxiliary interface rather than a limited input/output I/O space approach.

13. An enhanced auxiliary interface test method of claim 7 wherein the DUTs are peripheral component interconnect express (PCIe) Non Volatile Memory Express (NVMe) solid state drives (SSDs).

14. An enhanced auxiliary interface test system comprising:
a load board configured to couple with a plurality of devices under test (DUTs);
testing electronics configured to test the plurality of NVMe devices with a universal asynchronous receiver-transmitter (UART) interface, wherein the testing electronics are coupled to the load board;
a controller configured to direct testing of the DUTs, wherein the controller is coupled to the testing electronics; and
a flexible enhanced auxiliary interface configured to implement multiple paths to access a central processing unit (CPU) on the controller and enable testing of multiple NVMe devices in parallel, wherein the flexible enhanced auxiliary interface is supported by modifications to a field programmable gate array (FPGA), a driver, and a user space.

15. An enhanced auxiliary interface test system of claim 14 wherein a first number of DUTs to be to be tested in parallel is not constrained by input/output (I/O) space limitations of the CPU.

16. An enhanced auxiliary interface test system of claim 14 wherein the flexible enhanced auxiliary interface includes a memory mapped interface.

17. An enhanced auxiliary interface test system of claim 14 wherein the flexible enhanced auxiliary interface provides for test systems with multi-function devices that can work in an environment with more than one of the plurality of DUTs per the CPU.

Assignees

• Advantest Corp

Inventors

• Yuan Chi
• Malisic Srdjan

Classifications

• G06F11/2733 Primary

  Test interface between tester and unit under test · CPC title

• G06F13/1668

  Details of memory controller · CPC title

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F2213/0026

  PCI express · CPC title

• G06F13/4068 Primary

  Electrical coupling · CPC title