Time-domain filtering of gamma events

Patent metadata

Field	Value
Publication number	US-11898906-B2
Application number	US-202017626442-A
Country	US
Kind code	B2
Filing date	Jul 14, 2020
Priority date	Jul 19, 2019
Publication date	Feb 13, 2024
Grant date	Feb 13, 2024

Abstract

The present application relates generally to silicon photomultiplier (SiPM) detector arrays. In one aspect, there is a system including an array of cells each including a single-photon avalanche diode (SPAD) reverse-biased above a breakdown voltage of the SPAD. The system may further include a trigger network configured to generate pulses on a trigger line in response to SPADs of the array undergoing breakdown. The system may still further include a pulse-width filter configured to block pulses on the trigger line whose pulse width is less than a threshold width.

First claim

The invention claimed is:

1. An optical detector, comprising:
an array of cells each including a single-photon avalanche diode (SPAD) reverse-biased above a breakdown voltage of the SPAD;
a trigger network configured to generate pulses on a trigger line in response to SPADs of the array undergoing breakdown, wherein the trigger network comprises a network of OR gates connecting the cells of the array with the trigger line; and
a pulse-width filter configured to block pulses on the trigger line whose pulse width is less than a threshold width.

2. The optical detector of claim 1 further comprising timestamp circuitry configured to assign a timestamp to a trigger pulse that passes through the pulse-width filter.

3. The optical detector of claim 2 wherein the timestamp circuitry comprises a time-to-digital converter (TDC).

4. The optical detector of claim 1 further comprising integration circuitry configured to accumulate a count of SPAD breakdown events in the array of cells over an integration time period triggered by a trigger pulse that passes through the pulse-width filter.

5. The optical detector of claim 1 further comprising energy-based validation logic configured to validate the pulse on the trigger line that passes through the pulse-width filter, wherein in response to a failure of the validation, the optical detector resets.

6. The optical detector of claim 1 , wherein the pulse-width filter comprises:
a starved inverter comprising four transistors;
a gate oxide capacitor pair; and
an inverting Schmitt trigger configured to prevent voltage oscillations when a voltage on the capacitor pair reaches a predetermined voltage level.

7. The optical detector of claim 1 , wherein the pulse-width filter comprises:
a starved inverter;
a capacitor pair; and
an inverting Schmitt trigger.

8. The optical detector of claim 1 , wherein the trigger network further includes a pulse generator comprising a variable width pulse generator including:
a starved inverter configured to delay rising edges but not falling edges of the trigger signal;
a Schmitt trigger configured to receive an output of the starved inverter; and
an AND gate configured to output the pulse-width filtered signal by receiving:
(i) a first input signal comprising the trigger signal; and
(ii) a second input signal comprising an output signal of the Schmitt trigger.

9. The optical detector of claim 1 , wherein the trigger network further includes a pulse generator comprising a variable width pulse generator including:
a starved inverter configured to delay rising edges but not falling edges of the trigger signal;
a Schmitt trigger configured to receive an output of the starved inverter;
a static delay element configured to receive the trigger signal, and produce a statically delayed output signal by compensating for an internal delay of the Schmitt trigger; and
an AND gate configured to output the pulse-width filtered signal by receiving:
(i) a first input signal comprising the statically delayed output signal; and
(ii) a second input signal comprising an output signal of the Schmitt trigger.

10. The optical detector of claim 1 , wherein the trigger network further includes a pulse generator comprising a variable width pulse generator including:
a starved inverter configured to delay rising edges but not falling edges of the trigger signal;
a Schmitt trigger configured to receive an output of the starved inverter;
a plurality of static delay elements configured to receive the trigger signal;
a multiplexer configured to receive outputs of the plurality of static delay elements; and
an AND gate configured to output the pulse-width filtered signal by receiving:
(i) a first input signal comprising an output of the multiplexer; and
(ii) a second input signal comprising an output signal of the Schmitt trigger.

11. A Light Detection and Ranging (LIDAR) system including an optical detector as set forth in claim 1 .

12. A Positron Emission Tomography (PET) system comprising one or more PET detector rings comprising optical detectors as set forth in claim 1 .

13. The optical detector of claim 1 , wherein the pulse-width filter comprises:
a starved inverter comprising four transistors;
a gate oxide capacitor pair; and
an inverting Schmitt trigger configured to prevent voltage oscillations when a voltage on the capacitor pair reaches a predetermined voltage level.

14. A method, comprising:
with a trigger network, generating pulses on a trigger line in response to single-photon avalanche diode (SPADS) of the array undergoing breakdown, wherein the trigger network comprises a network of OR gates connecting cells of an array with the trigger line; and
with a pulse-width filter, blocking pulses on the trigger line whose pulse width is less than a threshold width.

15. The method of claim 14 , further comprising:
with timestamp circuitry, assigning a timestamp to a trigger pulse that passes through the pulse-width filter.

16. The method of claim 14 , further comprising:
with integration circuitry, accumulating a count of SPAD breakdown events in the array of cells over an integration time period triggered by a trigger pulse that passes through the pulse-width filter.

17. A trigger network for a silicon photomultiplier (SiPM) comprising an array of cells each including a single-photon avalanche diode (SPAD) reverse-biased above a breakdown voltage of the SPAD, the trigger network comprising:
a network of OR gates connecting the cells of the array with a trigger line, the network of OR gates generating pulse on the trigger line in response to SPADs of the array undergoing breakdown; and
a pulse-width filter configured to block pulses on the trigger line whose pulse width is less than a threshold width.

18. A Positron Emission Tomography (PET) system comprising one or more PET detector rings comprising a trigger network as set forth in claim 17 .

Assignees

• Avago Tech Int Sales Pte Lid

Inventors

• Frach Thomas
• Solf Torsten
• Groben Dennis

Classifications

• G01J1/44 Primary

  Electric circuits {(for command of an exposure part G03B7/02)} · CPC title

• H03K5/2463

  using diodes · CPC title

• H03K5/26 Primary

  the characteristic being duration, interval, position, frequency, or sequence · CPC title

• G01J2001/4406

  Plural ranges in circuit, e.g. switchable ranges; Adjusting sensitivity selecting gain values · CPC title

• G01J2001/4466

  Avalanche · CPC title