Electrostatic protection circuit and manufacturing method thereof, array substrate and display apparatus
US-2021082963-A1 · Mar 18, 2021 · US
US11895880B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11895880-B2 |
| Application number | US-202117307906-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 4, 2021 |
| Priority date | Nov 30, 2020 |
| Publication date | Feb 6, 2024 |
| Grant date | Feb 6, 2024 |
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A display device includes: a base layer including a first surface, and a second surface; a plurality of pixels on the first surface; and a plurality of first lines on the first surface. The base layer includes: a first base layer; an etch stop layer on the first base layer; a plurality of second lines on the etch stop layer; and a second base layer on the etch stop layer and the second lines. The first base layer, the etch stop layer, the second lines, and the second base layer are sequentially stacked, and the first lines are electrically connected to the second lines through first contact holes.
Opening claim text (preview).
What is claimed is: 1. A display device comprising: a base layer comprising a first surface, and a second surface; a plurality of pixels on the first surface; and a plurality of first lines on the first surface, wherein the base layer comprises: a first base layer; an etch stop layer on the first base layer; a plurality of second lines on the etch stop layer; and a second base layer on the etch stop layer and the second lines, wherein the first base layer, the etch stop layer, the second lines, and the second base layer are sequentially stacked, wherein the first lines are electrically connected to the second lines through first contact holes, and wherein the etch stop layer comprises conductive areas electrically connecting the second lines to a plurality of pads. 2. The display device of claim 1 , wherein the first base layer and the second base layer comprise a flexible plastic material. 3. The display device of claim 2 , wherein the plastic material is polyimide. 4. The display device of claim 1 , wherein a surface of the first base layer coincides with the second surface, and a surface of the second base layer coincides with the first surface. 5. The display device of claim 1 , further comprising a first barrier layer between the etch stop layer and the second base layer. 6. The display device of claim 5 , further comprising a second barrier layer on an opposite surface of the second base layer opposite to a surface of the second base layer contacting the first barrier layer, wherein the first barrier layer and the second barrier layer comprise a metal oxide or a metal nitride. 7. A display device comprising: a base layer comprising a first surface, and a second surface; a plurality of pixels on the first surface; a plurality of first lines on the first surface; and a plurality of pads on the second surface, wherein the base layer comprises: a first base layer; an etch stop layer on the first base layer; a plurality of second lines on the etch stop layer; and a second base layer on the etch stop layer and the second lines, wherein the first base layer, the etch stop layer, the second lines, and the second base layer are sequentially stacked, wherein the first lines are electrically connected to the second lines through first contact holes, and wherein the etch stop layer comprises doping areas at an area where the second lines and the pads overlap with each other in a thickness direction. 8. The display device of claim 7 , wherein the etch stop layer comprises a semiconductor material, and the doping areas comprise a conductive material. 9. The display device of claim 7 , wherein the etch stop layer comprises amorphous silicon, and the doping areas are doped with boron. 10. The display device of claim 7 , wherein the doping areas and the pads are electrically connected to each other through second contact holes. 11. The display device of claim 7 , further comprising a display area on the first surface, and configured to display an image, wherein the pixels are at the display area, and wherein the pads on the second surface overlap with the display area. 12. The display device of claim 7 , wherein the first lines comprise first gate lines and first data lines connected to the pixels. 13. The display device of claim 12 , wherein the second lines at least partially overlap with the first lines, and the second lines comprise second gate lines electrically connecting the first gate lines to some of the pads, and second data lines electrically connecting the first data lines to others of the pads. 14. The display device of claim 12 , wherein the pixels comprise: circuit elements connected to the first gate lines and the first data lines; and light emitting elements connected to the circuit elements.
Interconnections, e.g. scanning lines · CPC title
of multiple TFTs · CPC title
characterised by the compositions or shapes of the interlayer dielectrics · CPC title
characterised by materials, geometry or structure of the substrates · CPC title
wherein the TFTs are in active matrices · CPC title
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