Drive control system, control method and computer readable storage medium

US11895430B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11895430-B2
Application numberUS-202017288733-A
CountryUS
Kind codeB2
Filing dateMay 26, 2020
Priority dateJun 10, 2019
Publication dateFeb 6, 2024
Grant dateFeb 6, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A drive control system, a control method and a computer-readable storage medium, wherein the drive control system comprises: a system on chip, configured to receive video data and user operation instructions; a video data processor, electrically connected with the system on chip and configured to receive the video data and perform enhancement processing on the video data; an on-screen display data processor, electrically connected with the system on chip and configured to receive the user operation instructions and process the user operation instructions into corresponding on-screen display data; and a display drive circuit, electrically connected with the video data processor and the on-screen display data processor respectively and configured to receive video data subjected to enhancement processing and the on-screen display data and fuse the video data subjected to enhancement processing with the on-screen display data to drive a display panel for display according to fused data.

First claim

Opening claim text (preview).

What is claimed is: 1. A drive control system, comprising: a system on chip, configured to receive video data and user operation instructions; a video data processor, electrically connected with the system on chip and configured to receive the video data sent by the system on chip and perform enhancement processing on the video data; an on-screen display data processor, electrically connected with the system on chip and configured to receive the user operation instructions sent by the system on chip and process the user operation instructions into corresponding on-screen display data; and a display drive circuit, electrically connected with the video data processor and the on-screen display data processor respectively and configured to receive video data subjected to enhancement processing sent by the video data processor and the on-screen display data and fuse the video data subjected to enhancement processing with the on-screen display data to drive a display panel for display according to fused data; wherein the system on chip is further configured to: acquire a current resolution of the display panel and a current data architecture of an on-screen display data module in the on-screen display data processor; determine whether the current data architecture is matched with a data architecture of the on-screen display data module required by a current resolution or not; and send the data architecture of the on-screen display data module required by the current resolution to the on-screen display data processor, in response to determining that the current data architecture is not matched with the data architecture of the on-screen display data module required by the current resolution. 2. The drive control system according to claim 1 , wherein the system on chip is further configured to store a plurality of preset data architectures of the on-screen display data module. 3. The drive control system according to claim 1 , wherein the system on chip is further configured to: acquire a data architecture change instruction sent by a user; and generate and store a customized data architecture of the on-screen display data module according to the data architecture change instruction. 4. The drive control system according to claim 1 , wherein the data architecture comprises structural parameters of a graphical user interface displayed on the display panel. 5. The drive control system according to claim 1 , wherein the system on chip comprises a first system on chip and at least one second system on chip; the first system on chip is configured to receive the user operation instructions; and the first system on chip and each second system on chip are configured to receive the video data respectively. 6. The drive control system according to claim 1 , wherein the drive control system further comprises: a bypass signal receiving circuit, electrically connected with the video data processor and configured to receive a bypass video signal and send the bypass video signal to the video data processor; the video data processor is further configured to receive the bypass video signal and perform enhancement processing on the bypass video signal; and the display drive circuit is further configured to receive bypass video data subjected to enhancement processing sent by the video data processor. 7. A control method of the drive control system according to claim 1 , wherein the control method comprises: receiving, by the system on chip, video data and user operation instructions; sending, by the system on chip, the video data to the video data processor to trigger the video data processor to receive the video data and perform enhancement processing on the video data, and sending, by the system on chip, the user operation instructions to the on-screen display data processor to trigger the on-screen display data processor to receive the user operation instructions and process the user operation instructions into corresponding on-screen display data; receiving, by the display drive circuit, video data subjected to enhancement processing and the on-screen display data and fusing, by the display drive circuit, the video data subjected to enhancement processing with the on-screen display data; and driving, by the display drive circuit, the display panel for display according to fused data. 8. The control method according to claim 7 , wherein before receiving, by the system on chip, the video data and the user operation instructions, the control method further comprises: acquiring, by the system on chip, a current resolution of the display panel and a current data architecture of an on-screen display data module in the on-screen display data processor; determining whether the current data architecture is matched with a data architecture of the on-screen display data module required by a current resolution or not; and sending the data architecture of the on-screen display data module required by the current resolution to the on-screen display data processor, in response to determining that the current data architecture is not matched with the data architecture of the on-screen display data module required by the current resolution. 9. The control method according to claim 8 , wherein before receiving, by the system on chip, the video data and the user operation instructions, the control method further comprises: storing a plurality of preset data architectures of the on-screen display data module. 10. The control method according to claim 8 , wherein before receiving, by the system on chip, the video data and the user operation instructions, the control method further comprises: acquiring a data architecture change instruction sent by a user; and generating and storing a customized data architecture of the on-screen display data module according to the data architecture change instruction. 11. A non-transitory computer-readable storage medium, having a computer program stored thereon, wherein when the program is executed by a processor, the steps of the control method of the drive control system according to claim 7 are implemented. 12. The drive control system according to claim 2 , wherein the data architecture comprises structural parameters of a graphical user interface displayed on the display panel. 13. The drive control system according to claim 2 , wherein the system on chip comprises a first system on chip and at least one second system on chip; the first system on chip is configured to receive the user operation instructions; and the first system on chip and each second system on chip are configured to receive the video data respectively. 14. The drive control system according to claim 2 , wherein the drive control system further comprises: a bypass signal receiving circuit, electrically connected with the video data processor and configured to receive a bypass video signal and send the bypass video signal to the video data processor; the video data processor is further configured to receive the bypass video signal and perform enhancement processing on the bypass video signal; and the display drive circuit is further configured to receive bypass video data subjected to enhancement processing sent by the video data processor. 15. The drive control system according to claim 3 , wherein the data architecture comprises structural parameters of a graphical user interface displayed on the display panel. 16. The drive control system according to claim 3 , wherein the system on chip comprises a first system on chip and at least one second system on chip; the first system on chip is

Assignees

Inventors

Classifications

  • Circuit details of the additional information generator, e.g. details of the character or graphics signal generator, overlay mixing circuits · CPC title

  • G09G5/003Primary

    Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto (specific for a CRT G09G1/165; for a flat panel G09G3/2092) · CPC title

  • Control of mixing and/or overlay of colours in general (G09G5/022 and G09G5/024 take precedence) · CPC title

  • High-definition television systems · CPC title

  • High-definition television systems · CPC title

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What does patent US11895430B2 cover?
A drive control system, a control method and a computer-readable storage medium, wherein the drive control system comprises: a system on chip, configured to receive video data and user operation instructions; a video data processor, electrically connected with the system on chip and configured to receive the video data and perform enhancement processing on the video data; an on-screen display d…
Who is the assignee on this patent?
Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification H04N5/44504. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 06 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).