Motion model signaling

Patent metadata

Field	Value
Publication number	US-11895313-B2
Application number	US-202217585793-A
Country	US
Kind code	B2
Filing date	Jan 27, 2022
Priority date	Jul 17, 2018
Publication date	Feb 6, 2024
Grant date	Feb 6, 2024

Abstract

A method of determining one or more candidate prediction modes, the method comprises deriving, by a processor, a first indicator by parsing a bitstream, wherein the first indicator specifies whether any affine model is a candidate motion model for an image block in a preset area; determining, by the processor, that the first indicator is set to 1; deriving, by the processor and based on the determination that the first indicator is set to 1, a second indicator by parsing the bitstream, wherein the second indicator specifies whether a 6-parameter affine model is a candidate motion model for the image block; and determining, by the processor, one or more candidate prediction modes for the image block based on the first indicator and the second indicator.

First claim

The invention claimed is:

1. A method implemented by a video decoder and comprising:
receiving a video bitstream comprising a sequence parameter set (SPS) raw byte sequence payload (RBSP), wherein the SPS RBSP comprises a first SPS level flag, wherein the first SPS level flag equal to a first value specifies that an affine inter flag is present in coding unit syntax, and wherein the affine inter flag equal to the first value specifies that for a current coding unit, when decoding a P slice or a B slice, affine model based motion compensation is used to generate a predicted pixel of the current coding unit; and
decoding a video sequence from the video bitstream according to the first SPS level flag.

2. The method of claim 1 , wherein the first value is 1.

3. The method of claim 1 , wherein the video bitstream further comprises the coding unit syntax, and wherein the coding unit syntax comprises the affine inter flag.

4. The method of claim 1 , wherein the affine inter flag equal to a second value specifies that the current coding unit is not predicted by the affine model based motion compensation.

5. A method implemented by a video encoder and comprising:
generating a first sequence parameter set (SPS) level flag, wherein the first SPS level flag equal to a first value specifies that an affine inter flag is present in coding unit syntax, wherein the affine inter flag equal to the first value specifies that for a current coding unit, when decoding a P slice or a B slice, affine model based motion compensation is used to generate a predicted pixel for the current coding unit;
encoding the first SPS level flag into an SPS raw byte sequence payload (RBSP);
encoding the SPS RBSP into a video bitstream; and
storing the video bitstream for transmission to a video decoder.

6. The method of claim 5 , wherein the first value is 1.

7. The method of claim 5 , further comprising:
encoding the affine inter flag into the coding unit syntax; and
encoding the coding unit syntax into the video bitstream.

8. The method of claim 5 , wherein the affine inter flag equal to a second value specifies that the current coding unit is not predicted by the affine model based motion compensation.

9. A device comprising:
a memory configured to store instructions; and
a processor coupled to the memory and configured to execute the instructions to cause the device to:
receive a video bitstream comprising a sequence parameter set (SPS) raw byte sequence payload (RBSP), wherein the SPS RBSP comprises a first SPS level flag, wherein the first SPS level flag equal to a first value specifies that an affine inter flag is present in coding unit syntax, wherein the first SPS level flag equal to a second value specifies that the affine inter flag is not present in the coding unit syntax, and wherein the affine inter flag equal to the first value specifies that for a current coding unit, when decoding a P slice or a B slice, affine model based motion compensation is used to generate a predicted pixel of the current coding unit; and
decode a video sequence from the video bitstream according to the first SPS level flag.

10. The device of claim 9 , wherein the first value is 1 and the second value is 0.

11. The device of claim 9 , wherein the video bitstream further comprises the coding unit syntax, and wherein the coding unit syntax comprises the affine inter flag.

12. The device of claim 9 , wherein the affine inter flag equal to the second value specifies that the current coding unit is not predicted by the affine model based motion compensation.

13. A device comprising:
a memory configured to store instructions; and
a processor coupled to the memory and configured to execute the instructions to cause the device to:
generate a first sequence parameter set (SPS) level flag, wherein the first SPS level flag equal to a first value specifies that an affine inter flag is present in coding unit syntax, wherein the first SPS level flag equal to a second value specifies that the affine inter flag is not present in the coding unit syntax, wherein the affine inter flag equal to the first value specifies that for a current coding unit, when decoding a P slice or a B slice, affine model based motion compensation is used to generate a predicted pixel for the current coding unit;
encode the first SPS level flag into an SPS raw byte sequence payload (RBSP);
encode the SPS RBSP into a video bitstream; and
store the video bitstream for transmission to a video decoder.

14. The device of claim 13 , wherein the first value is 1 and the second value is 0.

15. The device of claim 13 , wherein the processor is further configured to execute the instructions to cause the device to:
encode the affine inter flag into the coding unit syntax; and
encode the coding unit syntax into the video bitstream.

16. The device of claim 13 , wherein the affine inter flag equal to the second value specifies that the current coding unit is not predicted by the affine model based motion compensation.

17. A computer program product comprising instructions that are stored on a non-transitory computer-readable medium and that, when executed by a processor, cause a device to:
receive a video bitstream comprising a sequence parameter set (SPS) raw byte sequence payload (RBSP), wherein the SPS RBSP comprises a first SPS level flag, wherein the first SPS level flag equal to a first value specifies that an affine inter flag is present in coding unit syntax, wherein the first SPS level flag equal to a second value specifies that the affine inter flag is not present in the coding unit syntax, and wherein the affine inter flag equal to the first value specifies that for a current coding unit, when decoding a P slice or a B slice, affine model based motion compensation is used to generate a predicted pixel of the current coding unit; and
decode a video sequence from the video bitstream according to the first SPS level flag.

18. The computer program product of claim 17 , wherein the first value is 1 and the second value is 0.

19. The computer program product of claim 17 , wherein the video bitstream further comprises the coding unit syntax, and wherein the coding unit syntax comprises the affine inter flag.

20. The computer program product of claim 17 , wherein the affine inter flag equal to the second value specifies that the current coding unit is not predicted by the affine model based motion compensation.

21. A computer program product comprising instructions that are stored on a non-transitory computer-readable medium and that, when executed by a processor, cause a device to:
generate a first sequence parameter set (SPS) level flag, wherein the first SPS level flag equal to a first value specifies that an affine inter flag is present in coding unit syntax, wherein the first SPS level flag equal to a second value specifies that the affine inter flag is not present in the coding unit syntax, wherein the affine inter flag equal to the first value specifies that for a current coding unit, when decoding a P slice or a B slice, affine model based motion compensation is used to generate a predicted pixel for the current coding unit;
encode the first SPS level flag into an SPS raw byte sequence payload (RBSP);
encode the SPS RBSP into a video bitstream; and
store the video bitstream for transmission to a video decoder.

22. The computer program product of claim 21 , wherein the first value is 1 and the second value is 0.

23. The

Assignees

• Huawei Tech Co Ltd

Inventors

• Ma Xiang
• Yang Haitao
• Chen Huanbang
• Chen Jianle

Classifications

• H04N19/132

  Sampling, masking or truncation of coding units, e.g. adaptive resampling, frame skipping, frame interpolation or high-frequency transform coefficient masking · CPC title

• H04N19/593

  involving spatial prediction techniques · CPC title

• H04N19/527

  Global motion vector estimation · CPC title

• H04N19/46 Primary

  Embedding additional information in the video signal during the compression process (H04N19/517, H04N19/68, H04N19/70 take precedence) · CPC title

• H04N19/159

  Prediction type, e.g. intra-frame, inter-frame or bidirectional frame prediction · CPC title