High electron mobility transistor and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-11894441-B2
Application number	US-202217745841-A
Country	US
Kind code	B2
Filing date	May 16, 2022
Priority date	Oct 9, 2019
Publication date	Feb 6, 2024
Grant date	Feb 6, 2024

Abstract

A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a first hard mask on the first barrier layer; removing the first hard mask and the first barrier layer to form a recess; forming a second barrier layer in the recess; and forming a p-type semiconductor layer on the second barrier layer.

First claim

What is claimed is:

1. A method for fabricating high electron mobility transistor (HEMT), comprising:
forming a buffer layer on a substrate;
forming a first barrier layer on the buffer layer;
forming a first hard mask on the first barrier layer;
removing the first hard mask and the first barrier layer to form a recess;
forming a second barrier layer in the recess while the first hard mask is on the first barrier layer and sidewalls of the first hard mask and the second barrier layer are aligned; and
forming a p-type semiconductor layer on the second barrier layer and directly contacting the first hard mask, wherein a topmost surface of the first hard mask is lower than a top surface of the p-type semiconductor layer.

2. The method of claim 1 , further comprising:
patterning the first hard mask, the first barrier layer, and the buffer layer;
forming a second hard mask on the first hard mask and sidewalls of the first barrier layer and the buffer layer;
forming the second barrier layer in the recess;
forming the p-type semiconductor layer on the second barrier layer;
removing the second hard mask;
forming a passivation layer on the first hard mask;
forming a gate electrode on the p-type semiconductor layer; and
forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.

3. The method of claim 1 , wherein the first barrier layer and the second barrier layer comprise Al x Ga 1-x N.

4. The method of claim 3 , wherein the first barrier layer and the second barrier layer comprise different concentrations of Al.

5. The method of claim 3 , wherein a concentration of Al of the second barrier layer is less than a concentration of Al of the first barrier layer.

6. The method of claim 1 , wherein a thickness of the second barrier layer is less than a thickness of the first barrier layer.

7. The method of claim 1 , wherein sidewalls of the p-type semiconductor layer and the second barrier layer are aligned.

Assignees

• United Microelectronics Corp

Inventors

• Chang Chun-Ming
• Huang Che-Hung
• Liao Wen-Jung
• Hou Chun-Liang

Classifications

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D30/475 Primary

  having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs · CPC title

• H10D30/015 Primary

  of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT · CPC title

• H10D62/852

  being Group III-V materials comprising three or more elements, e.g. AlGaN or InAsSbP · CPC title